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  1. I am working on Genesys 2 board for a while using Vivado 16.1 on Windows 10. It worked fine until yesterday. After rebooting my PC SDK/ Vivado is not detecting FPGA. I am not what has gone wrong suddenly. Please Help D
  2. I am using a Genesys 2 board. for connecting to PC via 1000T Ethernet. When I create a basic project as in link below, the echo_server works fine. https://reference.digilentinc.com/genesys2/gsmbs Above solution uses a AXI DMA in Ethernet and Microblaze path. With above solution, I add another DMA to connect to a fifo block. When I run SDK, I see that Ethernet path is broken and I see the following messages: TCP packets sent to port 6001 will be echoed back WARNING: Not a Marvell or TI Ethernet PHY. Please verify the initialization sequence link speed: 1000 Error set buf addr 80021D16 with 4 and 3, 2 Error set buf addr 80021F16 with 4 and 3, 2 Error set buf addr 80022116 with 4 and 3, 2 DHCP Timeout Configuring default IP of 192.168.1.10 Board IP: 192.168.1.10 Netmask : 255.255.255.0 Gateway : 192.168.1.1 TCP echo server started @ port 7 Error set buf addr 80022316 with 4 and 3, 2 Error set buf addr 80022516 with 4 and 3, 2 When I debugged the issue, I see that MM2S path of Ethernet DMA is blocked. FOllowing shows the register dump of AXI DMA. dma_reg 0x41E10000 : 0x01017002: 0x00015049: 0x80028100: 0x00000000 dma_reg 0x41E10010 : 0x80028100: 0x00000000: 0x00000000: 0x00000000 dma_reg 0x41E10020 : 0x00000000: 0x00000000: 0x00000000: 0x00000003 dma_reg 0x41E10030 : 0x01017002: 0x00010009: 0x80027B80: 0x00000000 dma_reg 0x41E10040 : 0x80027B80: 0x00000000: 0x00000000: 0x00000000 dma_reg 0x41E10050 : 0x00000000: 0x00000000: 0x00000000: 0x00000000 Can somebody help me overcoming this issue. Deepak
  3. I am following example: https://reference.digilentinc.com/genesys2/gsmbs with my new Genesys 2 board. However, Vivado gives bitstream generation error as: INFO: [Common 17-349] Got license for feature 'Implementation' and/or device 'xc7k325t' INFO: [Common 17-83] Releasing license: Implementation ERROR: [Common 17-69] Command failed: This design contains one or more cells for which bitstream generation is not permitted: system_i/axi_ethernet_0/U0/eth_mac/U0/tri_mode_ethernet_mac_i/bd_4bad_eth_mac_0_core (tri_mode_ethernet_mac_v9_0_4) I believe I should be able to use evaluation license to generate bitstream to program Genesys 2. Can somebody help?
  4. Where can I find some examples for transferring data from DDR on Genesys 2 board to PC via Ethernet. I see an example only for an echo-server. Thanks in advance.
  5. I found the solution at : https://forums.xilinx.com/t5/Xilinx-Boards-and-Kits/genesys-2-board-not-showing-up-in-Vivado-HL-2016-1/m-p/698807/highlight/false#M13275 Thanks, Dee
  6. I have recently purchased Genesys 2 board. While going through project described at https://reference.digilentinc.com/genesys2/gsmbs, I find following errors while synthesizing: ERROR: [Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xc7k325t'. Please run the Vivado License Manager for assistance in determining which features and devices are licensed for your system. I installed Vivado version 2016.1. The design edition, and it does not show Genesys 2 board. So, I had to use Kintex 7 KC705 (which uses Kintex 7 device as on Genesys 2 board) platform. I unstalled the software and reinstalled System Edition too. It also does not show Genesys 2 board. The status of licenses shows node locked license for OEM_7K325T_DesignEd, which I suppose is validity of Genesys 2 board. However, I installed Xilinx SDK ver 2014.4, and it runs the demo example file. Can you help me how to use board and device in my Vivado FPGA project? Thanks, Dee