a.gamez

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a.gamez last won the day on June 18 2016

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  1. Hi I'm writing a new board file based on the board.xml from the ARTY but with a modified SPI device. I want to use another pin as SS2 (select slave, or chip select, 2), in order to communicate with two SPI devices through the same bus. This is the diff between original board files and mine: --- a/new/board_files/newboard/1.0/preset.xml +++ b/new/board_files/newboard/1.0/preset.xml @@ -25,6 +25,7 @@ <user_parameter name="CONFIG.C_C_SCK_RATIO" value="16"/> <user_parameter name="CONFIG.C_USE_STARTUP" value="0"/> <user_parameter name="CONFIG.C_USE_STARTUP_INT" value="0"/> + <user_parameter name="CONFIG.C_NUM_SS_BITS" value="2"/> </user_parameters> </ip> </ip_preset> --- a/new/board_files/newboard/1.0/board.xml +++ b/new/board_files/newboard/1.0/board.xml @@ -579,19 +579,22 @@ <pin_map port_index="0" component_pin="spi_sclk_i"/> </pin_maps> </port_map> - <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in"> + <port_map logical_port="SS_I" physical_port="spi_ss_i" dir="in" left="1" right="0"> <pin_maps> - <pin_map port_index="0" component_pin="spi_ss_i"/> + <pin_map port_index="0" component_pin="spi_ss_i_0"/> + <pin_map port_index="1" component_pin="spi_ss_i_1"/> </pin_maps> </port_map> - <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out"> + <port_map logical_port="SS_O" physical_port="spi_ss_o" dir="out" left="1" right="0"> <pin_maps> - <pin_map port_index="0" component_pin="spi_ss_i"/> + <pin_map port_index="0" component_pin="spi_ss_i_0"/> + <pin_map port_index="1" component_pin="spi_ss_i_1"/> </pin_maps> </port_map> <port_map logical_port="SS_T" physical_port="spi_ss_t" dir="out"> <pin_maps> <pin_map port_index="0" component_pin="spi_ss_i"/> </pin_maps> </port_map> </port_maps> I haven't added another pin_map inside SS_T, as AXI QUAD SPI when configured with two slave devices, still only provides a single SS_T pin: Finally, I've replaced original spi_ss_i on part0_pins.xml with two lines, one defining loc pin of spi_ss_i_0 and one for spi_ss_i_1 (never mind exact pin numbering): - <pin index="93" name ="spi_ss_i" iostandard="LVCMOS33" loc="B20"/> + <pin index="93" name ="spi_ss_i_0" iostandard="LVCMOS33" loc="B20"/> + <pin index="94" name ="spi_ss_i_1" iostandard="LVCMOS33" loc="C20"/> However, Vivado won't let me use this board definitions with the following message: WARNING: [Board 49-69] Validation failed for board file vivado-boards/new/board_files/newboard/1.0/board.xml: Pin Map file does not provide LOC constraints for spi_ss_iCOMP : agamez:newboard:part0:1.0 What should I do?
  2. Hi, Thanks for the answer. Could you please forward to whomever is required that this would be a nice feature to have? Maybe for a future version. The ARTY shines in this regard.
  3. Hi! I've got an ARTY board and I find the USB connection incredible useful, as it allows to use only one connection to program the FPGA through JTAG while simultaneously act as an USB to serial converter. So, I also bought a JTAG-SMT2-NC to fit into a custom board and it's a very convenient way to program my FPGA, but... is it possible for it to act as the module that fits on the ARTY, and make it be recognized by the PC as a USB-serial converter, using its GPIO pins as the interface with the FPGA, as the ARTY does? That would be really great, but I think it's not possible, is it?
  4. Hi! Yes, I managed to solve the LEDs issue too. I had to use upstream linux kernel instead of that of Xilinx'... I definitely didn't expect that, but there's something wrong in there. I'd like to post a short guide explaning what I did, but I haven't had the time yet, sorry.
  5. Hi! I think I may have solved this! It seems that etherlite won't work under Linux if Enable Internal Loopback is unchecked. At least that's what's happening to me now Now I have a different problem, which is that before lots of changes, LEDs worked for me using gpio-led module, but now they don't. I guess I have screwed something up, but in a way it's funny that I got ethernet to work but broke something as simple as the LEDs... Best regards!
  6. Yes, I'm using arty board files. As you'll see, the design is very simple in fact. I made it starting off the same GSMB tutorial but modified the microblaze core so it could run linux and I added some of the board peripherics, such as SPI, GPIO, etc. Thanks a lot! mb_linux_bd.tcl eth.xdc
  7. I've followed the tutorial and I can ping the ARTY, it even gets its IP via DHCP, so the hardware works fine I've tried running iwlp example as above on my design and it doesn't work, so I guess we can assume that there is, in fact, something wrong with my IP design. However, I can't find what it is. Just to enumerate things, in case you notice something that is missing: I have an axi_timer with interrupt connected to concat/In0 and uartlite with interrupt connected to concat/In3. Both of them are a requisite of Linux. I also have an SPI core connected to the flash with its interrupt routed to concat/In2. By the way, I've been able to define device tree for the flash and it's working under Linux I have one 25 MHz clock routed to an external port named eth_ref_clk which is defined in an .xdc file to be routed to pin G18, as per GSMBS example. EthernetLite interrupt is also routed to concat/In1 There's nothing else I've found on emaclite code that uses any other value from the device tree. I've also compared the device tree with one that I know works on Avnet's LX9 board. In the end everything points to the IP design, but I can't find what's wrong...
  8. True! I've found it now there, thanks That's been a great idea! I just did that and that's been in fact the message that appears now, so the problem lies there, on finding PHY node. So, reading xilinx_emaclite.c code I found that I was missing phy-handle on device tree. So, my .dts file now looks like this: axi_ethernetlite_0: ethernet@40e00000 { compatible = "xlnx,xps-ethernetlite-1.00.a"; device_type = "network"; interrupt-parent = <&microblaze_0_axi_intc>; interrupts = <1 0>; reg = <0x40e00000 0x10000>; xlnx,duplex = <0x1>; xlnx,include-global-buffers = <0x1>; xlnx,include-internal-loopback = <0x0>; xlnx,include-mdio = <0x1>; xlnx,rx-ping-pong = <0x1>; xlnx,s-axi-id-width = <0x1>; xlnx,tx-ping-pong = <0x1>; xlnx,use-internal = <0x0>; phy-handle = <&phy0>; axi_ethernetlite_0_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@1 { device_type = "ethernet-phy"; reg = <1>; }; }; }; And after this, ethernet probes succesfully! xilinx_emaclite 40e00000.ethernet: Device Tree Probing libphy: Xilinx Emaclite MDIO: probed xilinx_emaclite 40e00000.ethernet: MAC address is now 00:0a:35:00:00:00 xilinx_emaclite 40e00000.ethernet: Xilinx EmacLite at 0x40E00000 mapped to 0xF0140000, irq=2 Sadly, there's still something wrong. Once I configure eth0 with an ip address (ifconfig eth0 192.168.1.222), the following keeps happening: xilinx_emaclite 40e00000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx xilinx_emaclite 40e00000.ethernet eth0: Link is Down xilinx_emaclite 40e00000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx xilinx_emaclite 40e00000.ethernet eth0: Link is Down xilinx_emaclite 40e00000.ethernet eth0: Link is Up - 100Mbps/Full - flow control rx/tx xilinx_emaclite 40e00000.ethernet eth0: Link is Down And it doesn't stop... So we've advanced a little, but I'm now stuck again :/ What do you reckon should be the next step?
  9. Hi again! I've found this document which, at page 9, stablishes what DP83848 PHY addr is https://download.beckhoff.com/download/Document/io/ethercat-development-products/an_phy_selection_guidev2.3.pdf You're definitely right that PHY address is 1, by that document. However, setting <reg> to 1 doesn't make any difference. I've also tried several values, ranging from PHY addr 0 to 4, and 16 to 20 with no luck, always with the same result. There must be something I'm missing, but I don't know what is it... I haven't any of this documented yet, but once I get this working I will surely do!
  10. I'm afraid that didn't work, exactly the same keeps happening. How do you know PHY address is 1? I haven't found any document that specifies it.
  11. Hi! I've implemented a Microblaze system on the ARTY board, which includes a Texas Instruments DP83848 PHY chip to manage ethernet communications. Xilkernel and example program 'echo server' works wonderfully, so any hardware issue is discarded. However, on linux (using both mainstream and xilinx' github repo), I can't get ethernetlite core to work. This is the info I can provide: axi_ethernetlite_0: ethernet@40e00000 { compatible = "xlnx,xps-ethernetlite-1.00.a"; device_type = "network"; interrupt-parent = <&microblaze_0_axi_intc>; interrupts = <1 0>; reg = <0x40e00000 0x10000>; xlnx,duplex = <0x1>; xlnx,include-global-buffers = <0x1>; xlnx,include-internal-loopback = <0x0>; xlnx,include-mdio = <0x1>; xlnx,rx-ping-pong = <0x1>; xlnx,s-axi-id-width = <0x1>; xlnx,tx-ping-pong = <0x1>; xlnx,use-internal = <0x0>; axi_ethernetlite_0_mdio: mdio { #address-cells = <1>; #size-cells = <0>; phy0: phy@0 { device_type = "ethernet-phy"; reg = <0>; }; }; }; phy0 section was written by me, as it was not provided by dts creation utility for the SDK. dmesg output: xilinx_emaclite 40e00000.ethernet: Device Tree Probing xilinx_emaclite 40e00000.ethernet: Failed to register mdio bus. xilinx_emaclite 40e00000.ethernet: error registering MDIO bus xilinx_emaclite 40e00000.ethernet: MAC address is now 00:0a:35:00:00:00 xilinx_emaclite 40e00000.ethernet: Xilinx EmacLite at 0x40E00000 mapped to 0xF0140000, irq=2 Relevant kernel config: CONFIG_NET_VENDOR_XILINX=y CONFIG_XILINX_EMACLITE=y CONFIG_PHYLIB=y CONFIG_DP83848_PHY=y CONFIG_XILINX_PHY=y eth0 interface appears, and ifconfig eth0 192.168.1.222 doesn't produce any error. However, no other host on the network can reach the ARTY nor viceversa, not by ping, nor by poking at any random port. Any ideas? Thanks!