In an effort to learn how to move network data to/from an FPGA I have taken the https://www.fpga4fun.com/10BASE-T.html ethernet project, rewrote it in VHDL and ported it to a Basys3. I also added a LOT of comments in the code to help explain the header information required for the packets, and I changed the way the IPV4 checksum was calculated in an attempt to make it more obvious with out it works. I used clock wizard IP to gen the 20MHz clock required for the project. This was all in Vivado 2019.1 but that only matters if you want to use the clock wizard IP that I attached. If you just generate your own clock IP, the vivado version you use will not matter. I learned a large amount (yet just scratched the surface) about ethernet, IPV4, and UDP to allow me to rewrite this project.
fpga4fun.com is a fantastic site, even after it appears to have been abandoned years ago. Thank you so much Jean P. Nicolle for leaving your fantastic site online for us.
UDP_Tx.vhd
Basys3_Master.xdc
clk_wiz_0.xcix
FlyingBlindOnARocketCycle got a reaction from D@n in Ethernet/IPV4/UDP Basys3
