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FlyingBlindOnARocketCycle

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Everything posted by FlyingBlindOnARocketCycle

  1. I have a PC running UDP receiving software that is always listening. The Basys3 project I posted is wired to one pair of Tx pins on a short piece of CAT5 and plugs into a LAN switch on my home network. I can see on my PC the UDP packets I'm receiving from the FPGA and the data is correct. All of this is explained in great detail at the link I provided in my first post https://www.fpga4fun.com/10BASE-T0.html It seemed silly to retype all of the information that is found at the link. I clearly stated that my project was a VHDL version of that project and ported to Basys3. I wonder how much of this post you have really examined before providing an opinion on its lack of merit?
  2. Would your objection be alleviated if the project had been titled "Ethernet/IPV4/UDP Tx from a Basys3" ? The code I posted is complete and operates for Tx. I also have a link to the source project on fpga4fun.com The VHDL I posted along with its comments are documenting much of what I learned while converting the original Verilog project to VHDL. As I doubt there are any Basys3 owners who haven't looked through the Digilent forum for education and inspiration, I feel this project, even in its Tx only state, is completely appropriate here. It's not as if I am trying to sell this as IP. I'm just leaving some bread crumbs along my journey to help any others who stumble upon my path. Thank you for your input.
  3. Is this insane? Can I wire a PMOD port, specifically pins JA10 and JA4 as a differential receive port for a UDP project? The brilliant guy who wrote this on fpga4fun.com built a circuit to generate a common mode input. If I attempt to wire RD+ and RD- directly to a differential pin pair in the PMOD port, am I wasting my time? Damaging my Basys3? I'm thinking about starting by hooking it up with a project that is designed just to run an ILA and see what happens. I am expecting these receive signals to be plus and minus 2.5v. I would like to wire those pins to an IBUFDS. Please talk me out of this if I'm about to do something very stupid. I fear I am about to embark on one of those "hold my beer" and "hey watch this" moments.
  4. I just noticed I wrote an incorrect comment in the XDC file I uploaded. The notes on what pins I am using are not correct. I chose these two pins because the FPGA chip has these two as a dedicated differential pair. You can see this when you open synthesis and view the Package Pins window. H1 is the P pin and J1 is the N pin of a pair. At the slow 10BASE-t speeds this detail might not matter but why not use pins that are placed inside the FPGA specifically with the option of acting as a differential pair? So thats what I did. #Sch name = JA7 set_property PACKAGE_PIN H1 [get_ports Ethernet_TDp] set_property IOSTANDARD LVCMOS33 [get_ports Ethernet_TDp] #Sch name = JA1 set_property PACKAGE_PIN J1 [get_ports Ethernet_TDm] set_property IOSTANDARD LVCMOS33 [get_ports Ethernet_TDm]
  5. In an effort to learn how to move network data to/from an FPGA I have taken the https://www.fpga4fun.com/10BASE-T.html ethernet project, rewrote it in VHDL and ported it to a Basys3. I also added a LOT of comments in the code to help explain the header information required for the packets, and I changed the way the IPV4 checksum was calculated in an attempt to make it more obvious with out it works. I used clock wizard IP to gen the 20MHz clock required for the project. This was all in Vivado 2019.1 but that only matters if you want to use the clock wizard IP that I attached. If you just generate your own clock IP, the vivado version you use will not matter. I learned a large amount (yet just scratched the surface) about ethernet, IPV4, and UDP to allow me to rewrite this project. fpga4fun.com is a fantastic site, even after it appears to have been abandoned years ago. Thank you so much Jean P. Nicolle for leaving your fantastic site online for us. UDP_Tx.vhd Basys3_Master.xdc clk_wiz_0.xcix
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