FlyingBlindOnARocketCycle

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  1. Is the basys 3 MGT is not routed for use?

    Curious. Why choose to not route the more powerful of the I/O on the chip?
  2. Is the basys 3 MGT is not routed for use?

    It appears to me that the MGT bank on the Basys 3 is not routed for use per the schematic. Is that correct? Thanks
  3. Is simple math not so simple? 1/(500.0E-9 + (100.0E-9 * N)

    "the LED's blur and dim as they move back and forth " dude! that sounds really cool. Now I MUST do that. As far as controlled speed of the simple back and forth LED, I have accomplished that already. My VHDL uses the left/right button to inc/dec the speed and the seven segments display an integer 1-15 as an indication of the speed. The 1-15 setting is arbitrary as it only indicates the slowest to fastest and not a true hz. I also use the middle button as a go/stop button for the LED sweep and when its not sweeping it just blinks at your selected rate on LED 0. The top button toggles between an LED sweeping back and forth or all LED's on with a dark spot sweeping back and forth. I was considering making a game. use the switches to turn on LED's. the left/right buttons to set the sweep/blink rate a go button and a "whack a mole" button. If you click it while the sweeping led is at the same spot as the switched on LED, then that LED turns off. Maybe a pattern flashes a could times on the seven segs. So far my VHDL is kind of scatter brained. I have a package I made and put a to_sev_seg(int) function in there. Maybe integer was not a good choice bit the function cleaned up my code a ton. My current speed control is done with integers. I have a set quantity that I inc/dec with the left/right buttons. I made a seven segment controller component that should come in handy with the basys3 on most occasions. component seven_seg_driver is Port ( clk : in STD_LOGIC; -- input clock of 100MHz gets divided down to 240Hz so each 7 seg has a refresh of 60hz rst : in STD_LOGIC; -- not used yet N_in : in integer range 0 to 9; dec_p : in STD_LOGIC; -- not used yet select_dis : in integer range 0 to 5; -- 0 = off 1-4 = display on segment bank 1 or 2 or 3 or 4, 5 = display up to a 4 digit integer with leading zeros not displayed d_out : out STD_LOGIC_VECTOR (11 downto 0) --11 downto 6 are 7 seg data, 5 is the dec point, 4 downto 0 are sev seg bank on/off controll ); I could set other select_dis integers to do more stuff. Like the hit indicator pattern in Whack a mole. Getting this working made me think a clk speed component would be handy also. And that's where I started trying to do simple/not so simple math. But now all I can think about is blurring LED's as they sweep. so thanks for that.... :S
  4. Is simple math not so simple? 1/(500.0E-9 + (100.0E-9 * N)

    we're gonna need a bigger boat. after reading Dan's link it became apperant that I will have to find another way around. I have been told before that a look up table is often the path of least resistance. I'll might as learn how to implement that now. thanks fellas
  5. NEXYS4 Artix-7 board

    CRAP! I bought PmodWiFi for the sole purpose of learning to integrate it on my Basys3. Foolishly I thought that Pmod ports available on the Basys3 meant it was compatible with Pmod devices.
  6. SFP over vc709 Board

    MOHIT You should try the Xilinx forum to find help on the VC709 as that product. The digilent guys are very helpful but the Xilinx forum will have a bigger VC709 user community as well as Xilinx staff who know your board. Also, Xilinx has a tutorials that you can down load for the VC709 that also have example projects with XDC's. http://www.xilinx.com/products/boards-and-kits/dk-v7-vc709-g.html?resultsTablePreSelect=documenttype:Example The IBERT tutorial downloads even use Bank113 on the VC709. You could get the proper XDC from there. Also note I think you have to jumper SMA jacks J31 and J32 to SMA Jacks J25 and J26 to feed a clock to bank 113 refclk 1. Or do you have an external clock wired up? Good luck
  7. Is simple math not so simple? 1/(500.0E-9 + (100.0E-9 * N)

    Short version: N = 0 to 19 reset <= 1/(500.0E-9 + (100.0E-9 * N) I can't get this to work. I receiver errors. found '0' definitions of operator "*", cannot detgermine exact overloaded matching definition for "*" found '0' definitions of operator "+", cannot detgermine exact overloaded matching definition for "+" found '0' definitions of operator "/", cannot detgermine exact overloaded matching definition for "/" Long version: I am playing with my Basys3. I made a Hello World which in my case is Blink LED 101. I can display numbers on the seven segment and increase/decrease them with button presses. The number represents the speed at which the LED's will race back and forth like Kit from Night Rider or, depending on your age, Cylon . I would like to control this with a bit more exactness. I am trying to make a component that I can instantiate and provided the 100MHz sys clock along with a value (0 to 19). Then I have a signal, "count" that resets to 0 when its value reaches my reset value as well as toggles a bit. (new_hz_clk <= not new_hz_clk) If I want to have frequencies of 50Hz to 240Hz in increments of 10Hz based on a value of N (0 - 19) the math works out to: reset <= 1/(500.0E-9 + (100.0E-9 * N) I am struggling to figure out this math in VHDL.
  8. Is learn.digilent.com dead?

    It appears as though all the VHDL components have dead links. Maybe I have a PC/Network issue or maybe all the links are dead. https://learn.digilentinc.com/classroom/vhdlcomponents/
  9. How to configure basys3 board thorough vivado.?

    Its the cord! Its the cord! Its the cord! Its the cord! Its the cord! Its the cord! Its the cord! Its the cord! Someone had mentioned that a poor quality usb cable can be an issue. I tried a few different usb cables and thought that I must have some different problem. Until one day.... I grabbed yet another cable and (mind explosion!!!!) the usb cable and Bruce Willis were dead the whole time. NOTE: The good usb cable fit noticeably tighter than all the others.
  10. Basys3 Xilinx University Lab 3 - No led's

    It is functioning in 2015.4 also. Odd about the problems with 2016.1. There appear to be problems with usb/serial driver and 2016.1 also. I seem to be able to have multiple version of Vivado installed and can open the version I need. Thanks a lot for all the effort to this issue.
  11. How to configure basys3 board thorough vivado.?

    Well this is not my only problem so I'll give it a shot. I'm also having no luck with 2016.1 and some Digilent/Xilinx lab material that doesn't function. Its kind of annoying to change versions as a fix because, like most people who would be on a website like this, I hate loose ends and things that don't work. But if 2015.4 get me a stable system, I'll live with it. I'll give it a shot. Thanks
  12. How to configure basys3 board thorough vivado.?

    Im on 2016.1 Thanks
  13. This warning appears every time I connect to a target in the hardware manager. INFO: [Labtools 27-1434] Device xc7a35t (JTAG device index = 0) is programmed with a design that has no supported debug core(s) in it. WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-bscan <C_USER_SCAN_CHAIN scan_chain_number>" to detect the debug hub at User Scan Chain of 2 or 4. To determine the user scan chain setting, open the implemented design and use: get_property C_USER_SCAN_CHAIN [get_debug_cores dbg_hub]. Thanks
  14. How to configure basys3 board thorough vivado.?

    I spoke to soon. I am having continuous trouble with the usb/jtag port on the Basys3. I have had to uninstall and reinstall the drivers several times. It works, and then it doesn't....
  15. Basys3 Xilinx University Lab 3 - No led's

    Have you guys made any headway into identifying the issue with this lab?