• Content Count

  • Joined

  • Last visited

About FlyingBlindOnARocketCycle

  • Rank
    Frequent Visitor

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. I have a PC running UDP receiving software that is always listening. The Basys3 project I posted is wired to one pair of Tx pins on a short piece of CAT5 and plugs into a LAN switch on my home network. I can see on my PC the UDP packets I'm receiving from the FPGA and the data is correct. All of this is explained in great detail at the link I provided in my first post It seemed silly to retype all of the information that is found at the link. I clearly stated that my project was a VHDL version of that project and ported to Basys3. I
  2. Would your objection be alleviated if the project had been titled "Ethernet/IPV4/UDP Tx from a Basys3" ? The code I posted is complete and operates for Tx. I also have a link to the source project on The VHDL I posted along with its comments are documenting much of what I learned while converting the original Verilog project to VHDL. As I doubt there are any Basys3 owners who haven't looked through the Digilent forum for education and inspiration, I feel this project, even in its Tx only state, is completely appropriate here. It's not as if I am trying to sell this as IP. I'm ju
  3. Is this insane? Can I wire a PMOD port, specifically pins JA10 and JA4 as a differential receive port for a UDP project? The brilliant guy who wrote this on built a circuit to generate a common mode input. If I attempt to wire RD+ and RD- directly to a differential pin pair in the PMOD port, am I wasting my time? Damaging my Basys3? I'm thinking about starting by hooking it up with a project that is designed just to run an ILA and see what happens. I am expecting these receive signals to be plus and minus 2.5v. I would like to wire those pins to an IBUFDS. Please talk
  4. I just noticed I wrote an incorrect comment in the XDC file I uploaded. The notes on what pins I am using are not correct. I chose these two pins because the FPGA chip has these two as a dedicated differential pair. You can see this when you open synthesis and view the Package Pins window. H1 is the P pin and J1 is the N pin of a pair. At the slow 10BASE-t speeds this detail might not matter but why not use pins that are placed inside the FPGA specifically with the option of acting as a differential pair? So thats what I did. #Sch name = JA7 set_property PACKAGE_PIN H1 [get_ports Ethe
  5. In an effort to learn how to move network data to/from an FPGA I have taken the ethernet project, rewrote it in VHDL and ported it to a Basys3. I also added a LOT of comments in the code to help explain the header information required for the packets, and I changed the way the IPV4 checksum was calculated in an attempt to make it more obvious with out it works. I used clock wizard IP to gen the 20MHz clock required for the project. This was all in Vivado 2019.1 but that only matters if you want to use the clock wizard IP that I attached. If you just g
  6. @JColvin I'm confused. Is your design_1VHDL.tcl not identical to the uSD.tcl I posted?
  7. If there is a comparability list somewhere, it would be nice to know about it. Thanks
  8. Digilent has created a LOT of tutorials. It seems like the questions I have for the forum usually end up with a link to a polished Digilent tutorial that I didn't know existed. The tutorial maybe for a specific piece of hardware that I am not using but the information learned may be transferable. Is there a spot on Digilent's web servers where I can browse the tutorial content before I go to the forum with a question? A tutorial index would be very time saving.
  9. Thank you for going deep into this. I posted a tcl script for the project in my thread where I ask for help with the Pmod SD. Should we migrate back to that thread for discussion of the Pmod SD on a Basys 3?
  10. Yes. Pmod SD issues were worked through here with @JColvin The Pmod SD can not fit the Basys 3.
  11. Attempting to build a project with Pmod SD (no Pmod Wi-Fi) is to big to fit in the Basys 3.
  12. Hello again @Ana-Maria Balas After watching this video which says the Pmod wifi can function an any Artix 7 board and having a Basys 3 (Artix 7) I then purchased the Pmod wifi and Pmod SD. While attempting to learn my way though this it appears that the comparability statement in the video may be misleading. Having trouble with the Pmod SD @JColvin said it would not fit on the Basys 3 and I would If I understand what you are saying, as the Basys 3 has no external RAM, the Pmod SD not compatible. Is this correct?
  13. Hi @Ana-Maria Balas Thanks for bringing the microblaze tutorial to my attention. You have helped me recently with a Xilinx microblaze tutorial, Lab 4, UG940. I will study the digilent link you provided as I notice digilent tutorials usually have more details than a Xilinx tutorial. When I re-read the steps you mention ,0.1 -0.6, I do wonder if there should be a step 0.7? Should the tutorial say to export the hardware design with the bitstream included?
  14. Hello I am attempting to follow this but I am confused about section 2.3. It says to place all the application code in DDR. The Basys3 has no external memory but for the SPI flash. From a SPI flash description from an Arty reference, it says but when I read the Xilinx answer record 63605, it says on step 5. Create helloworld application and link to DDR (in the linker script make sure that this application is executing from DDR) Can someone explain to me how to do this all in the SPI flash? Do I need to somehow set that up in my block design in? I do have the QSPI in my blo
  15. This tutorial has you create an application project in the SDK but I don't see where it tells you to export the hardware design from Vivado. Am I missing something?