FlyingBlindOnARocketCycle

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  1. @JColvin I'm confused. Is your design_1VHDL.tcl not identical to the uSD.tcl I posted?
  2. If there is a comparability list somewhere, it would be nice to know about it. Thanks
  3. Digilent has created a LOT of tutorials. It seems like the questions I have for the forum usually end up with a link to a polished Digilent tutorial that I didn't know existed. The tutorial maybe for a specific piece of hardware that I am not using but the information learned may be transferable. Is there a spot on Digilent's web servers where I can browse the tutorial content before I go to the forum with a question? A tutorial index would be very time saving.
  4. Thank you for going deep into this. I posted a tcl script for the project in my thread where I ask for help with the Pmod SD. Should we migrate back to that thread for discussion of the Pmod SD on a Basys 3?
  5. Yes. Pmod SD issues were worked through here with @JColvin The Pmod SD can not fit the Basys 3.
  6. Attempting to build a project with Pmod SD (no Pmod Wi-Fi) is to big to fit in the Basys 3.
  7. Hello again @Ana-Maria Balas After watching this video which says the Pmod wifi can function an any Artix 7 board and having a Basys 3 (Artix 7) I then purchased the Pmod wifi and Pmod SD. While attempting to learn my way though this it appears that the comparability statement in the video may be misleading. Having trouble with the Pmod SD @JColvin said it would not fit on the Basys 3 and I would If I understand what you are saying, as the Basys 3 has no external RAM, the Pmod SD not compatible. Is this correct?
  8. Hi @Ana-Maria Balas Thanks for bringing the microblaze tutorial to my attention. You have helped me recently with a Xilinx microblaze tutorial, Lab 4, UG940. I will study the digilent link you provided as I notice digilent tutorials usually have more details than a Xilinx tutorial. When I re-read the steps you mention ,0.1 -0.6, I do wonder if there should be a step 0.7? Should the tutorial say to export the hardware design with the bitstream included?
  9. Hello I am attempting to follow this but I am confused about section 2.3. It says to place all the application code in DDR. The Basys3 has no external memory but for the SPI flash. From a SPI flash description from an Arty reference, it says but when I read the Xilinx answer record 63605, it says on step 5. Create helloworld application and link to DDR (in the linker script make sure that this application is executing from DDR) Can someone explain to me how to do this all in the SPI flash? Do I need to somehow set that up in my block design in? I do have the QSPI in my block design already but it is not available to me as an option in the linker script window.
  10. This tutorial has you create an application project in the SDK but I don't see where it tells you to export the hardware design from Vivado. Am I missing something?
  11. Hey @JColvin Do you think you could post your Basys3 project with the functional Pmod SD? Then I could sift through and see what I'm doing different/wrong. Maybe a block design tcl? I attached my latest attempt. It was done in Vivado 2018.2 with the latest Digilent library (2019_1) Thanks FBOARC Edit: Well hang on to your flipflops darn it! When I rebuild this project, from my OWN stinking project tcl, it builds with different warnings and does not spit out the "BOARD_PART_PIN cannot be assigned to more than one port" errors that I get when I create the project originally. I get this [filemgmt 20-1673] Unlinking is not permitted for the source file: 'H:/microSD/microSD.srcs/sources_1/bd/uSD_bd/uSD_bd.bd' and I get the "critical" warnings this IP was packaged for a different board blah blah blah. I see the IP design out-of-contect Module Runs all say they are using cached IP results which I don't understand a I started the build from the tcl as a brand new project. I do think this altered behavior is a clue. I don't know what to do with this clue.... uSD.tcl
  12. Hi @JColvin Thank you for taking the time to create a bitstream for the Pmod SD. Are you saying that when you did this in "Vivado 2018.2 and did not have to do anything to change .xdc values" that you created a bitstream with no errors? When I try in vivado 2018.2, it does create a bitstream as I mentioned but I also get errors. I am using the 2018.2-1 rev of the Digilent IP library. Also I should mention that I have Vivado project settings to default to VHDL as opposed to Verilog. Would that make a difference at all? I am comfortable in VHDL and struggle in Verilog so I like it when Vivado makes the top wrapper for me in VHDL. The above statement is very unfortunate for me. When the youtube states at the beginning "if you don't have the arty you can also use any of our artix 7 fpga boards..." I believed I had acquired all the hardware I needed to implement this project. I'm trying to use this as a learning experience and it seems to be throwing up road blocks. At the end of the day I don't really care about the SD Pmod I bought as I only bought it because I was lead to believe it was required to use the Wifi Pmod in accordance with the tutorial video. With only a fingertip hold of what I'm doing here, I fear the alternative paths I need to follow like "a SPI bootloader application for the SDK project" are going to lead to endless frustration. Until attempting this project I had never opened the SDK. The tutorial says External memory? The Basys3 has none. What does it mean when referencing the SPI flash. I have used SPI flash to load a design file (MCS) but I have never had to implemented it as part of my design. I always had vivado build the file in the "Generate Memory Configuration File" window. Please advise further. By the way, the video uses an Arty. There are two version of the Arty. I wonder if the Arty version with the 35T chip would be equally incapable as the Basys3?
  13. I am having layers of problems with the Pmod MicroSD. My ultimate goal is to get through the wifi example on youtube with a Basys 3. Today I am just trying to do the "hello world" demo for the micro SD Pmod. Issues: [Common 17-69] Command failed: BOARD_PART_PIN cannot be assigned to more than one port ["f:/microSD.srcs/sources_1/bd/microSD_bd/ip/microSD_bd_PmodSD_0_0/microSD_bd_PmodSD_0_0_board.xdc":7] I get this error for 4 pins set_property BOARD_PIN {JB7} [get_ports Pmod_out_pin7_t] set_property BOARD_PIN {JB8} [get_ports Pmod_out_pin8_t] set_property BOARD_PIN {JB9} [get_ports Pmod_out_pin9_t] set_property BOARD_PIN {JB10} [get_ports Pmod_out_pin10_t] Vivado does finish making the bitstream. I then push on incase it works anyway. In the SDK I get another error. 12:28:33 **** Incremental Build of configuration Debug for project uSD **** make all 'Building target: uSD.elf' 'Invoking: MicroBlaze g++ linker' mb-g++ -Wl,-T -Wl,../src/lscript.ld -L../../uSD_bsp/microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "uSD.elf" ./src/main.o -Wl,--start-group,-lxil,-lgcc,-lc,-lstdc++,--end-group c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: uSD.elf section `.text' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 159832 bytes collect2.exe: error: ld returned 1 exit status make: *** [uSD.elf] Error 1 12:28:35 Build Finished (took 1s.389ms) Without really knowing what I'm doing, I read the error and think I need to allocate more local memory to the microblaze. "overflowed by 159832 bytes" I then open up my block design and try to customize the microblaze but see no place in change the memory it is allocated. I used the address editor and increase the allocated memory for the dlmb to 128K and then the ilmb to 128K. If I try 256K for each the validation fails. Then after this I get a slightly better SDK error. 13:13:22 **** Auto Build of configuration Debug for project uSD **** make all 'Building file: ../src/main.cc' 'Invoking: MicroBlaze g++ compiler' mb-g++ -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/main.o" -I../../uSD_bsp/microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/main.d" -MT"src/main.o" -o "src/main.o" "../src/main.cc" 'Finished building: ../src/main.cc' ' ' 'Building target: uSD.elf' 'Invoking: MicroBlaze g++ linker' mb-g++ -Wl,-T -Wl,../src/lscript.ld -L../../uSD_bsp/microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -Wl,--gc-sections -o "uSD.elf" ./src/main.o -Wl,--start-group,-lxil,-lgcc,-lc,-lstdc++,--end-group c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: uSD.elf section `.text' will not fit in region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' c:/xilinx/sdk/2018.2/gnu/microblaze/nt/bin/../lib/gcc/microblaze-xilinx-elf/7.2.0/../../../../microblaze-xilinx-elf/bin/ld.exe: region `microblaze_0_local_memory_ilmb_bram_if_cntlr_Mem_microblaze_0_local_memory_dlmb_bram_if_cntlr_Mem' overflowed by 61528 bytes collect2.exe: error: ld returned 1 exit status make: *** [uSD.elf] Error 1 13:13:25 Build Finished (took 2s.724ms) My over flow is down to 61528 bytes. I am doing all this by following the IPI tutorial and just adding the PmodSD to it. here and here Thanks FBOARC PS I am using Vivado 2018.2 as that is the version in the tutorial.
  14. Tells me PmodWIFI is packaged with board value arty and to update my basys3 to the arty. I am confused. Well hang on a second. It finished generating a bitstream and I see no critical warnings in the project summary. In fact if I tell vivado to discard user generated messages in the messages window, the project has no indication of critical warnings at all. Still confused but closer to my goal.
  15. I Finally figure it out! In the microblaze settings in vivado you have to set "microblaze debug module interface = Extended" to enable cross-trigger with a microblaze design. The debug target settings in the software IDE will not have a cross-trigger check box when using a microblaze as it would if using a real processor.