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  1. Is there a way to prevent the JTAG-SMT2-NC USB pull-ups from activating (or delay activation)? When do the pullups become active? To provide more background, I am designing a system where the FPGA will power up and configure prior to USB host. The USB connection will be "device down" -- no cable present. I have concern that the USB D+ pullup present on the JTAG-SMT2-NC (by USB spec requirements) may cause power on issues for the (unpowered) USB host. Possible solutions I am considering: Prevent pullup on USB D+ until USB Host is powered up. I have a control signal to know when the USB host is powered up. This may not be possible based on design of JTAG-SMT2 Power up JTAG-SMT2-NC only when USB host is powered up. May cause issues at JTAG-SMT2-NC due to pullups present on JTAG signals in the FPGA applied when JTAG-SMT2-NC is not yet powered Related: May Vref be powered prior to Vdd? (This way Vref is powered with FPGA configuration bank Vcco, and Vdd is powered up after USB host is powered). Are there any allowable power up sequences for VDD/VREF that allow JTAG side of the device to power up without powering up the USB side until a later time?