Gra

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  1. Looks like you have 6 errors, but you can't see them because you have only elected to display warning.. Gra
  2. Hello Richa, I've flipped designs between different FPGA families many times, its not as simple as it first appears, as I guess you know it can be a real can of worms. Id be looking for issues in the following areas... You talked about changes to the memory where the program runs from, I'd re-visits that. If you've changed from a Spartan3 to an Artix 7 you will need to update your VHDL to make it work efficiently on the new architecture. If you miss this step (at best) it can under perform (at worst) the design may behave completely differently on the new device, s
  3. Hi Allan, I see you've got the right idea about the clock paths, and you've been re-formatting your hdl syntax too, it now looks much more like that recommend by Xilinx. If you are not doing so already, I'd recommend you take a look at the constraints, and note that there is a sequence that they should be in, its like this... Constraints Sequence ## Timing Assertions Section # Primary clocks # Virtual clocks # Generated clocks # Clock Groups # Bus Skew constraints # Input and output delay constraints ## Timing Exceptions Section # False Paths # Max Delay / Min D
  4. Hello Allan, Your post said you were new to FPGAs and VHDL, despite this you had figured out that the tool was dropping parts of your design during syntheses, and you knew which parts it was dropping too. That's impressive for someone new to this, its fundamental, and that's why I assumed you were probably an experienced engineer working in a new area. I guess you know this... There is a principle that is used by the educated and experienced, its called "see one, do one, teach one". That's what I did, I simply showed you how I'd do something on the FPGA, I think you'll take a l
  5. Hi Allan, Just had to pop out and walk the dog... I've updated your file, attached. I've put some schematics on there so you can see the changes I made, don't forget to take that line out of the xdc too. Does that make it do what you wanted it to do? I've just noticed your "counter process" too, synthesis may just take that as an instruction to invert CLK_4_RAW, possibly clock it with CLK_IN, is that bit working? Kind Regards Graham RAD_counter.vhd
  6. Hi Allan Also, It did pass Synthesis after I added set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets HAM_IN_IBUF]; into the xdc (not a recommended thing to do) Kind Regards Graham
  7. Hi Allan Ugly is fine, but it will mess with the syntheses quite a lot, using a clock buffer with an enable would do the trick. Kind Regards Graham
  8. Hi Allan, I think the first thing you should do with the project is stop gateing HAM_IN with a clock. (cycles_raw <= HAM_IN and clk_cycles). Kind Regards Graham
  9. I’m a little confused about the I/O direction of the USB-UART bridge on the Arty A7 35. The following is how I think its rigged, does this look right to you guys? The uart_rxd_out (port name in the xdc): This is data received by the UART from the USB side of the bridge, so it’s an output from the UART side of the bridge and an input to the FPGA. The uart_txd_in ( port name in the xdc): This is data transmitted by the UART over the bridge to the USB, so its an input on the UART side of the bridge and an output from the FPGA. Or do I have it the wrong way around
  10. Hello Pavel, I think you may be trying to carry out a partial FPGA re-configuration. I was doing this some time ago,, so cant remember exact details.. I guess it was maybe 7 years ago with ISE, and I did a little bit of this with Vivado a couple of years ago, but the recent stuff was mainly to do with configuring a small part of the FPGA (then activating it) to meet critical system interface timing demands, I guess that was partial configuration rather than partial re-configuration πŸ™‚ . Funny how we go from, re-configure to save silicone to pre-configure to save time eh Pavel πŸ™‚ P
  11. Hi RipCityBassWorks.. I wanted to know how it was going so I thought I'd send you the UG link.. πŸ™‚ ... You know how engineers are, we always want to know what the problem was πŸ™‚ In my experience a float often goes high or low, it doesn't really flip frequently over time, but I guess it may do that with this device. Floating wouldn't change a registered value, assuming all the buttons are doing this, perhaps you have no bank power, are the slide switches doing the same thing? Gra
  12. Hi RipCityBassWorks.. You will find it in Xilinx UG912 page 308 https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug912-vivado-properties.pdf Gra
  13. Sounds like something is floating. I suggest you test it by.. Use VHDL to simply connect the buttons to the LED's, check your on the right pins πŸ™‚.. If it's still floating around then add a pulldown to each button net in your XDC you could then change to pullups and check the results. Gra
  14. Hi MTlabhishek, I took a really quick look at the schematic, looks like the max power out on that converter is a little under 5W, so you shouldn't be seeing 2 amps in at 5V. I'd start by re-loading a reference design and measure the current again. Your design can change the power drawn, design errors can also cause large currents to flow. Gra