Gra

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  1. I see, thanks jpeyron
  2. I’m a little confused about the I/O direction of the USB-UART bridge on the Arty A7 35. The following is how I think its rigged, does this look right to you guys? The uart_rxd_out (port name in the xdc): This is data received by the UART from the USB side of the bridge, so it’s an output from the UART side of the bridge and an input to the FPGA. The uart_txd_in ( port name in the xdc): This is data transmitted by the UART over the bridge to the USB, so its an input on the UART side of the bridge and an output from the FPGA. Or do I have it the wrong way around? Thanks for your help Gra
  3. Hello Pavel, I think you may be trying to carry out a partial FPGA re-configuration. I was doing this some time ago,, so cant remember exact details.. I guess it was maybe 7 years ago with ISE, and I did a little bit of this with Vivado a couple of years ago, but the recent stuff was mainly to do with configuring a small part of the FPGA (then activating it) to meet critical system interface timing demands, I guess that was partial configuration rather than partial re-configuration 🙂 . Funny how we go from, re-configure to save silicone to pre-configure to save time eh Pavel 🙂 Perhaps a good place to look is search the Xilinx site for "Partial reconfiguration controller" I recall using it and I think there a a number of tools, all Xilinx IP.. Hope that helps Gra
  4. Hi RipCityBassWorks.. I wanted to know how it was going so I thought I'd send you the UG link.. 🙂 ... You know how engineers are, we always want to know what the problem was 🙂 In my experience a float often goes high or low, it doesn't really flip frequently over time, but I guess it may do that with this device. Floating wouldn't change a registered value, assuming all the buttons are doing this, perhaps you have no bank power, are the slide switches doing the same thing? Gra
  5. Hi RipCityBassWorks.. You will find it in Xilinx UG912 page 308 https://www.xilinx.com/support/documentation/sw_manuals/xilinx2018_2/ug912-vivado-properties.pdf Gra
  6. Sounds like something is floating. I suggest you test it by.. Use VHDL to simply connect the buttons to the LED's, check your on the right pins 🙂.. If it's still floating around then add a pulldown to each button net in your XDC you could then change to pullups and check the results. Gra
  7. Hi MTlabhishek, I took a really quick look at the schematic, looks like the max power out on that converter is a little under 5W, so you shouldn't be seeing 2 amps in at 5V. I'd start by re-loading a reference design and measure the current again. Your design can change the power drawn, design errors can also cause large currents to flow. Gra
  8. Piasa, it was actually an example to show a loop, not to demonstrate the best way to describe a shift register. Gra
  9. its just a way of reducing the amount of HDL you have to type Here is an example, say you want to describe a shift register, you have an input and an output data pin, say input_port : std_logic; output_port : std_logic; you are going to need some flipflops for your shift register, lets have 8, you need an input to each flipflop and an output from each flipflop, here are some sigs for that input_signal : std_logic_vector(7 downto 0); output_signal : std_logic_vector(7 downto 0); then you need to describe the flipflops, Process (....) begin if (clk ‘event and clk = ‘1’) then output_signal <= input_signal; end if; end process; Now you have 8 individual flipflops with inputs... input_signal(0) input_signal(1) input_signal(2) input_signal(3) input_signal(4) input_signal(5) input_signal(6) input_signal(7) and outputs.... output_signal(0) output_signal(1) output_signal(2) output_signal(3) output_signal(4) output_signal(5) output_signal(6) output_signal(7) So to get your shift register you will need to connect the output of the first flipfloip to the input of the second flipflop and so on.... Then connect your i/o ports, so something like this input_signal(0) <= input_port input_signal(1) <=output_signal(0) input_signal(2) <=output_signal(1) input_signal(3) <=output_signal(2) input_signal(4) <=output_signal(3) input_signal(5) <=output_signal(4) input_signal(6) <=output_signal(5) input_signal(7) <=output_signal(6) output_port <= output_signal(7) All a loop does is compress the notation, the above would do something like this... i = 1 to 7 input_signal(0) <= input_port input_signal(i) <=output_signal(i-1) output_port <= output_signal(7) Useful notation if the shift register was much bigger, or you wanted to change the size easily, also useful in big repetitive circuits like hand crafted filters. Not helpful when you are working in teams and they are used for something as simple as the above, as you can see its easier to read the long-hand description than a loop.. Hope that helps... Gra
  10. Hi Jamie Just to add... A recent design job I did had most of the components that you mentioned. It landed on a 20nm Kintex Ultrascale. Gra
  11. Hi Jamie, I would initially put a “bare bones” type of design together with no physical hardware, get the PCIe blocks and transceivers into the design, stick some filters, clocking etc in there and built it. If you are buying off the shelf hardware rather than building your own, you can look at the various options on the market... Get the physical constraints file and device types for those options then stick that into the mix and go for timing closure (which is often the most challenging step on designs like the one your describing). Simulate, refine close the timing. Once you are happy, buy the right hardware and start the debug process with integrated logic analysers etc. In your position I’d hire an experienced FPGA engineer, it will save you time and money. Gra
  12. Gra

    Spartan 3 Starter Board Help

    Hi Nick, You use ISE to develop, as part of ISE suite you get a tool called impact, I think the Spartan 3 was supported right up to ISE 14xx (check before you download). You can configure the FPGA with a bit file or configure the platform flash with something like an mcs file, bit file is volatile, the mcs will configure the fpag at start up. When you plug it in you should see both devices on your jtag chain (in impact) you click on the device and prog it. loads of info here https://reference.digilentinc.com/spartan-3:spartan-3 Note on a more modern Digilent board you don't need to buy a jtag cable Gra
  13. Gra

    FPGA file types

    Thanks guys... and D@n the article was very useful, thanks. Gra
  14. Gra

    FPGA file types

    I’m a little bit stuck, can anyone help me with this. In a project I’m looking at there are 3 file types, mcs bit and fw .bit files (fpga config volatile) .mcs goes on the non volatile device, used to configure the FPGA at startup .fw file .... I don’t know, if I had to guess I’d say, maybe the software instructions for an embedded processor, but that's just a guess. Can anyone tell me just what the .fw file does? Many Thanks