paulleons

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  1. Hi, Do Digilent offer any reference design for ethernet related example or a completed project of the above Ethernet - Microblaze server wiki ? Some figures (which shows the parameters used in the design, eg: section 3.2 of wiki) are not very clear. Also, connections made by the tool after running Run Block Automation and Run Connection Automation are slightly different from my design either due to a different version of Vivado or due to some other reason. A reference design would be a very helpful in this case. Thanks, Paul
  2. Thanks Mikel and JColvi. I tried your code and unfortunately, it did not work. I created a small wrapper code for the code provided and the design behaved the same as before(attached wrapper code along with the post). On-chip data capture using ILA core was also done and the capture is also attached with the post. It shows that PDM data is indeed fed back to PWM output to audio-out. However, I cannot hear anything from the audio output. I was wondering if the code provided was ever tested in actual hardware.If so, could I get access to that Xilinx project? Also, if figure 28 in the reference guide is wrong, it would be great if you could provide another figure along with a detailed description so that it's becomes more clear. Wrapper code: module microphone_audio_out_top ( input logic clk_i , input logic rstn_i , output logic pdm_clk_o , input logic pdm_data_i , output logic pdm_lrsel_o , output logic pwm_audio_o , output logic pwm_sdaudio_o ); Mic_Demo Mic_Demo_inst ( .anout (pwm_audio_o ), .ampSD (pwm_sdaudio_o ), .sclk (pdm_clk_o ), .ncs (pdm_lrsel_o ), .sdata (pdm_data_i ), .clk (clk_i ) ); endmodule microphone_audio_out_top.sv
  3. Hi, I am trying to use microphone and audio-out of Nexys 4 board from Digilant. I have the following questions: 1. I implemented the refernce audio design provided by digilant which records audio for 5 seconds and play-back the recording from RAM. I noticed that both the interface namely micro-phone and audio-out operate on same clock domain and PDM interface. I tried to by-pass the RAM by directly connecting micro-phone output to audio-input (after 2 pipeline stages). But the design does not work as expected. Any thoughts on this will be appreciated. 2. I would also like to process the data received in FPGA via PDM. How do I convert this to N-bit digital signal of certain frequency which corresponding to the analog signal ? Should I do a moving average over certain terms. If so, how many terms? The figure 28 in the user-guide doesn't seem to be very clear. Thanks, Paul