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  1. Thanks. If you don't mind, I would like to understand the reasons behind putting the DDR3 pins in a .prj file (which may just be my lack of Xilinx tool experience). If the other pins are in the .xdc file, why are the DDR pins handled differently? .prj files don't seem to be a normal file for Vivado and aren't generated in the normal compile flow. Thanks for any of this background.
  2. I'm trying to compile the Xilinx example file for the MIG generated DDR3 controller in Vivado 2015.4. I used the .ucf file to generate the controller just fine. But when I look at the .xdc file, I don't see the DDR3 pins. I see all the other interfaces I believe, except for the DDR3. Won't this prevent a design that uses the DDR3 from compiling?