Ciprian

Digilent Staff
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Everything posted by Ciprian

  1. As far as I can tell from your code, you are continuously reinitialize and reconfigure the XSysMon (the XADC driver). During this process, which is redundant, you are loosing a lot of samples. Try this instead: #include <stdio.h> #include "xparameters.h" #include "platform.h" #include "xsysmon.h" #include "xil_printf.h" #include "xstatus.h" #include "xuartlite.h" #define UARTLITE_DEVICE_ID XPAR_UARTLITE_0_DEVICE_ID #define SYSMON_DEVICE_ID XPAR_SYSMON_0_DEVICE_ID #define UART_BUFFER_SIZE 16 #define NUMBER_OF_SAMPLES 4500 int main() { static XSysMon SysMonInst; /* System Monitor driver instance */ unsigned int ReceivedCount = 0; unsigned char RecvBuffer[UART_BUFFER_SIZE]; XUartLite UartLite; unsigned int channel = 3; int Status; XSysMon_Config *ConfigPtr; XSysMon *SysMonInstPtr = &SysMonInst; int *sample; //External memory address to store samples sample=(int *)0x60000000; init_platform(); Status = XUartLite_Initialize(&UartLite, UARTLITE_DEVICE_ID); ReceivedCount = 0; while(ReceivedCount==0){ ReceivedCount = XUartLite_Recv(&UartLite, (unsigned char *) RecvBuffer, 1); } ConfigPtr = XSysMon_LookupConfig(SYSMON_DEVICE_ID); if (ConfigPtr == NULL) { return XST_FAILURE; } XSysMon_CfgInitialize(SysMonInstPtr, ConfigPtr, ConfigPtr->BaseAddress); XSysMon_SetAvg(SysMonInstPtr, XSM_AVG_0_SAMPLES); XSysMon_SetAdcClkDivisor(SysMonInstPtr, 39); XSysMon_SetSequencerMode(SysMonInstPtr, XSM_SEQ_MODE_SINGCHAN); XSysMon_SetCalibEnables(SysMonInstPtr, XSM_CFR1_CAL_PS_GAIN_OFFSET_MASK | XSM_CFR1_CAL_ADC_GAIN_OFFSET_MASK); Status= XSysMon_SetSingleChParams(SysMonInstPtr, XSM_CH_AUX_MIN+channel, FALSE, FALSE, TRUE); if(Status != XST_SUCCESS) { return XST_FAILURE; } /* * Disable all the alarms in the Configuration Register 1. */ XSysMon_SetAlarmEnables(SysMonInstPtr, 0x0); while(1){ /* * Wait till the End of conversion */ //print("Capturing\n\r"); for(int i=0;i<NUMBER_OF_SAMPLES;i++){ XSysMon_GetStatus(SysMonInstPtr); /* Clear the old status */ while ((XSysMon_GetStatus(SysMonInstPtr) & XSM_SR_EOC_MASK) != XSM_SR_EOC_MASK); //Four last bits are noise *(sample+i) = XSysMon_GetAdcData(SysMonInstPtr, XSM_CH_AUX_MIN+channel); } //print("Finish capture\n\r"); //xil_printf("samples=np.array(["); for(int i=0;i<NUMBER_OF_SAMPLES-1;i++){ xil_printf("%d,",*(sample+i)); } xil_printf("%d\r\n",*(sample+NUMBER_OF_SAMPLES-1)); xil_printf("end\n"); } cleanup_platform(); return 0; }
  2. @HeroGian Your question is somewhat tricky. It is doable on an ARM but as far as I can gather it's not dynamic, you either start without caches and then everything moves slower or you continue using caches. The dynamical approach is somewhat tricky because you risk freezing your OS. I you want to try that you can find more info here: https://forums.xilinx.com/t5/Embedded-Linux/how-disable-cache-in-Linux/td-p/740556 There might be a better way to do it. What you actually want is just a hardware accelerated memcpy in the DDR, you could try to handle this like an DMA transfer in to DDR from the PL and use a coherency function for it. These are kernel space specific functions so I guess you will have to wirte a kernel driver for it. I strongly suggest reading about continuous memory (CMA) and coherent data transfers + the ACP port of the Zynq before proceeding. Here is a link which might give you an insight in to what and why I suggest this. https://forums.xilinx.com/t5/Embedded-Processor-System-Design/Cache-Flushing/td-p/635653 https://forums.xilinx.com/t5/Embedded-Processor-System-Design/XC7Z010-can-I-automatically-invalidate-cache-with-my-PL-to-DDR/td-p/715220 Although you are using a Zynq, there might be some useful information in the ZynqMP wiki by xilinx about what you need. https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842098/Zynq+UltraScale+MPSoC+Cache+Coherency Sorry for not being able to give you a more coherent and straight forward answer, what you are attempting is tricky. Good Luck, -Ciprian
  3. Ciprian

    PCAM OV5640 Power

    Hi @Sduru, These are BSP errors you will have to regenerate the bsp. Just right click on it in the project explorer (on the left of the main SDK windows) and hit Re-generate BSP sources. These are common xilinx SDK errors, not specific to this project. -Ciprian
  4. Hi @daeroro, #define SPI_DEV "/dev/spidev32766.0" Judging by the .dtsi this should be something else... probably something like spidev1.0. You will need to change to the right device name. To determine which is the right name please run ls /dev/ | grep spi on the running petalinux target. -Ciprian
  5. @ahmedengr.bilal Sorry I have no experience with that, you will need to look it up. -Ciprian
  6. Ciprian

    PCAM OV5640 Power

    Hi @Sduru, In order to see data transfers on the AXI-Stream interface which is connected to the PCAM you will need to configure the PCAM and enable the DMA transfers to do so. This is accomplished using the SDK, therefor you will need to program and monitor the ILA as well as run the SDK program to see any changes on the ILA. I'm guessing that you have a problem with running the code which would explain why you don't see the menu on the console or any traffic on the ILA. I'm guessing that your terminal is set up properly (although using COM1 is unusual), because you mentioned that you ran a hello world project and it displayed the message on the terminal, which leaves us with the possibility that you either have an error running the code in SDK or that there is a bug which does not allow you to get to the menu part of the PCAM code. To test this please put a xil_printf("hello world\n"); at the beginning of the main function and check if it is displayed. -Ciprian
  7. Hi @ahmedengr.bilal, Like I mentioned in the previous post there is no HDMI output from the Linux side, neither the embedded rootFS provided by petalinux nor the kernel configuration we give out is set to accommodate this feature. Regarding the missing media-ctl and v4l2-ctl, you have not activated the v4l-utils in the rootfs configuration of the petalinux. to do this you need to navigate to your petalinux project folder and run: petalinux-config -c rootfs Once the menu appears you need to go to Filesystem Packages->misc->v4l-utils and activate: v4l-utils, libv4l, media-ctl. Rebuild the whole project and it should be working now. -Ciprian
  8. HI @osmaan_khan, To clarify on xillybus and XADC, we have never configured the design which they provide, therefore we don't know how to add the XADC IP to it and interface it with their linux kerne and rootfs. Regarding the VCC and the GND pins, the PMOD connector JA can be configured as XADC or can be used as a simple PMOD connector (following the PMOD standard you need VCC and GND), when using it in a XADC configuration the VCC and the GND can be ignored. All the information on how the XADC works, configurations and limitations can be found in ug480 form xilinx. For instance, you cannot measure a voltage grater 1V using the XADC, you will have to scale your voltage in order to measure it with the XADC (maybe use a voltage divider, it depends on you circuit). The XADC is a Xilinx IP which is configurable both from the IP configuration window in Vivado and trough some registers using the AXI-Lite interface, with a xilinx kernel you should have access to it if the XADC driver is active in the kernel and if the .dts is configured to include the IP. We cannot help you with this, unfortunately; you will have to ask the support team from xillybus about how to manage this. - Ciprian
  9. Hi @flying, There is a lot to unpack here. Firstly I would like to draw your attention to the fact that this post was originally started by malkauns regarding the porting of the petalinux project with PCAM capabilities to the Zybo Z7-10 board, very similar to a previous topic which you have started. If you follow the steps in the previous post by vicentiu you should have the HW configuration finished by vivado, and then all you need to run is: petalinux-config --get-hw-description=<PATH-TO-HDF-DIRECTORY> petalinux-build petalinux-package --boot --force --fsbl images/linux/zynq_fsbl.elf --fpga images/linux/system_wrapper.bit --u-boot In the Petalinux-Zybo-Z7-20 project and you should have everything working the way it's described in the projects readme. Secondly (although off topic), regarding the "the "desktop" of the Petalinux.", our petalinux project so far has no GUI in the FS(file system) therefore you will not be able to see anything on the HDMI display. The HDMI is currently configured as a pass trough, in the petalinux project, at 720p; which means everything that is sent via the HDMI RX connector is forwarded to the HDMI TX connector without processing. All of this is routed trough the FPGA, meaning that without programming the .bit into the FPGA, the HDMI will not work. For more details on this please refer to the block diagram of the Zybo-Z7-20-base-linux which is an intuitive description of what I explained here. Lastly, regarding the rest of the questions (also off topic), most are answered by reading trough the petalinux user guide ug1144 which describes how petalinux works and the workflow. I would also recommend reading up on how the Zynq processor is used in bare-metal and the role of the ps7_init files, the .bit, the .hdf and the BOOT.bin.Unfortunately going in to detail about these, would be hard without making it in to a tutorial or a step by step guide with page long explanations at every step. I hope this helped clarify some of your queries. -Ciprian
  10. Hi @Luighi Vitón, Thanks for your reply and for your heads up, I'm glad you managed to get it working. --Ciprian
  11. Hi @fangzr, It seems to me that you teacher has asked you to write a kernel driver from scratch (more or less) for a wireless module. Depending on what he expects the driver module to contain, you could either write only the driver for the module it self (RTL8812au for example) or the module and the corresponding dependencies which will make development very hard because you will need to integrate a lot in to the kernel. I have unfortunately no experience with WiFi kernel driver development, but I would take it one step at a time. Starting with understanding kernel drivers and what their role is and then looking over the WiFi kernel interface, you can read about this here, understanding the structure of it and then starting to write my own driver by looking at already existing one (RT3070 for example). I would also recommend to read about the various forms of kernel debugging like KGDB and how to do that or Xilinx has a brief step by step "tutorial" here about using Xilinx SDK for kernel debugging. It's no an easy task, Good Luck. -Ciprian
  12. Hi @fangzr, I am not familiar with RTL8812au, but I managed to set up a ath9k dongle driver for the Zybo Z7-20 with petalinux. For the ATH9K it's easier because it has the driver in the kernel you just need to activate it. Regarding the RTL8812au all I can tell you from experience is that some Wireless dongles need additional firmware, like the ATH9K, which will be loaded in to the wireless automatically over USB, provided you set up your USB port to identify mass storage devices. These should be copied in to the corresponding folder on the rootfs of your target. Another critical issue is the driver dependencies, some Wireless drivers need to have certain Kernel drivers loaded in order for them to work, like the MAC80211 stack in the Kernel for instance. Please make sure that your driver is not depended on anything else. Based on the log you have sent us, I would start with this. -Ciprian
  13. Hi @Mingfei, If you are referring to Arty-Z7-XX-hdmi-out, where XX is either 10 or 20, demo then you have series of solutions to make it work faster. Before I go in to detail regarding this let's talk a bit what the demo actually does. It basically reads one frame (dispCtrl.framePtr[dispCtrl.curFrame]) and then takes every pixel and inverts it in to the output frame (dispCtrl.framePtr[nextFrame]) this is a software approach (based on how DemoInvertFrame() is written) which means that it will depend on the processor how fast it can manage the data. Therefor stuff like printing text on the console (like printf("Volage.....)) will slow it down. As for the solutions there are 2 way to try and speed it up: 1. Software, VDMA has a feature called frame buffer parking you can read all about it in the User Guide (PG020 for v6.3), it basically parks the output frame on one buffer and lets you edit the other 2 frames without interrupting the video out stream. This will increase your out put to 50 fps but the refresh rate of what you want to do, the actual processing, will still only work at 5 frames. 2. Hardware, you could take advantage of your FPGA and write a IP core which does the inversion in HW thus offloading the task from the processor and getting to almost no processing delay; this of course means you will have to redesign your project. I would recommend writing the IP in HLS because it's easier and placing it at the output stage be teen the VDMA and the Subset Convertor. -Ciprian
  14. Hi @Luighi Vitón, I'm not sure it's a HDMI issue, have you tried to use X11 over SSH do you get the same result? -Ciprian
  15. Hi @AndyCap, Unfortunately I don't have the time to look in to this but judging by what you said I would look in to the IP driver of the audio system <kernel>/sound/soc/adi/axi-i2s.c (as far as I remember), how the buffers are handled in regards to the DMA transfer. The issue might be that full and the empty flags are nor properly handled in the driver or in the HDL IP. Sorry for not being able to help more. -Ciprian
  16. Hi, We are planning to update our project to 2018.3 but we don't have a precise release date for it yet. If it's not mandatory to use 2018.3 please stick with 2017.4 with this project for the time being. -Ciprian
  17. Ciprian

    Digital Twin

    Hi @Kris Persyn, It depends on how you manage your resources, driving immersive visuals on a HDMI display can be done in multiple ways at different resolutions, some are PL taxing others are DDR taxing; you could generate entire frame buffers in PL or PS or you could find a optimal algorithm to change just the previous frame or you could allocate a high number of frame buffers and then run them in a loop. It also depends on how math lab synthesizes the IP you will need to add to your design. If you design your project properly and don't aim for a resolution higher more 720p( I'm being conservative, we managed to drive the HDMI at 1080p with processing filters without a problem) I think it should be enough for what you want to do, resource wise. My suggestion, download and install Vivado, download and install the board files, create and implement your project look at the resource consumption and then buy a board. - Ciprian
  18. Ciprian

    zybo hdmi to vga out

    Hello @Gourav, Unfortunately the issue could be in multiple locations and it's hard to determine this from the block diagram, it's probably a small bug either in the block design or in the HLS IP. Either way please send the archive with project so that I can look over it. Thank you -Ciprian
  19. Try adding this: &i2c0 { clock-frequency = <100000>; status = "okay"; }; Here: <petalinux_project>/project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi -Ciprian
  20. I'm not sure about this but I would look in to the HPD signal, as far as I know in the Nexys Video demo is set up so that the HPD is a pass-trough signal which might interfere with the zybo z7 design. I will ask our colleague who has more experience in HDMI if he has some input regarding your question. -Ciprian
  21. Hi @Amin, It depends on what you are planning to do. If you only need a Linux running on your Zybo Z7-20, then I can give you our pre-build BOOT.bin, kernel+rootfs images. This approach is based on our Demo HW platform, you will have the benefit of a lot of IPs in the design which allows a very versatile approach to the board, unfortunately this will not allow you to add any new IP to the design. If you want to build you own platform and base the on board Linux on it then you will need to install petalinux on linux(I recommend Ubuntu) and build/customize it the way you want, @jpeyron sent you the links for this in the previous post. -Ciprian
  22. Hi @kotra sharmila, Please follow the steps provided in this read me to modify/create your project. Please kkep in mind the following NOTE at step 12 - Ciprian
  23. Hi @Jeremy, Petalinux creates a series of .dts files based on your Hardware Description File, these are overwritten by the system-user.dtsi located in: <petalinux project root>/project-spec/meta-user/recipes-bsp/device-tree/files and the automatically created device tree files are here: <petalinux project root>/components/plnx_workspace/device-tree/device-tree-generation The petalinux project for Zybo-z7-20 from our github is configured based on this Vivado project which contains VTC, HDMI, I2S and other IPs. Consequently the system-user.dtsi is used to redefine parameters of the automatically generated device tree files. What you will have to do is rewrite the system-user.dtsi to suit your needs. Basically as far as I can tell from your .hdf you only have one axi gpio in the PL. This means that you will have to remove all the IP's from it which are not in your PL(you can see a list of them in the error you sent us) and if you want to use a different driver for your axi gpio IP you will have to add it to the system-user.dtsi and make the changes there -Ciprian
  24. Hi @Ben B, Regarding your question on using Zybo Z7-20 to capture HDMI signals. It is possible and using UIO is also an option, but because we are using the VDMA to get the Video signal it's better to use a DMA driver. Unfortunately Xilinx does not provide a complete DMA driver for any of their DMA IPs, therefore I have been using this DMA driver which includes the VDMA functionality as well. To make things as easy as possible, I generated a example project for you with the VDMA used to capture video streams and OpenCV functions to write a *.bmp file. What you need to do in order to get it working is: 1. load the HDMI2BMP.elf to /home/root on your rootfs portion of your board 2. after the board boots you need to load the axi_dma_driver root@Zybo-Z7-20:~# insmod /lib/modules/4.9.0-xilinx-v2017.4/extra/xilinx-axidma.ko 3. run the HDMI2BMP.elf This will generate a test.bmp in /home/root with the captured image. The source file for the app is in the SDK folder. Changes which I had to do to the original petalinux project are: - create a new module in petalinux petalinux-create -t modules -n xilinx-axidma --enable - copy the necessary file to Petalinux-Zybo-Z7-20/Zybo-Z7-20/project-spec/meta-user/recipes-modules/xilinx-axidma/files and update the MAKE file and the xilinx-axidma.bb - update the system-user.dtsi in /Petalinux-Zybo-Z7-20/Zybo-Z7-20/project-spec/meta-user/recipes-bsp/device-tree/files - write the demo program Hope this helps. -Ciprian Zybo-Z7-20-HDMI-RX_peta.zip
  25. It is not recommended to install petalinux anywhere else then "/opt/pkg/petalinux", we encountered similar issues when installing petalinux in other locations... That's why we usually specify in our petalinux project how to install petalinux and where. -Ciprian