Ciprian

Digilent Staff
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Everything posted by Ciprian

  1. Hi @wpless If you just want to run it and make no changes to it you can use Digilents releases for it. Here: https://github.com/Digilent/Eclypse-Z7/releases v0.2 is the latest and it will contain and .img file which you can flash to your SDcard and have everything set up for you. Digilent, as far as I know, doesn't provide SDcards with the Eclypse-Z7 "box" but you can have a fully functional debian running on the board, without rebuild, with the above link. -Ciprian
  2. Ciprian

    USB audio on PYNQ-Z1

    Hi @tara901, Depending on what your end goal is you will have to enable the CONFIG_SND_USB_* (most probably CONFIG_SND_USB_AUDIO, but I can't be sure because I don't own your adapter to test it out) or the CONFIG_USB_AUDIO in the Linux kernel. Both require ALSA and USB to be active in the kernel. I won't go in to details on what either the CONFIG_SND_USB_* or CONFIG_USB_AUDIO does, the best place to read up on it is on the ALSA wiki where you can find more details about what they are. I must warn you here, ALSA is very finicky, it might not work as expected from the begging. Unf
  3. Ciprian

    USB audio on PYNQ-Z1

    Hi @tara901, I need to know some more info before we go further. What Linux are you using on the target and where did you get it? What USB-Mic are you trying to use? -Ciprian
  4. There seams to be a misunderstanding either on my part or on yours. To clarify things here is what I understand so far: You recently switched to Ubuntu 18.04 LTE on the PC (host) and you noticed that the console is not working, you tried to create a helloworld project in standalone mode (aka bare-metal) for your Zedboard (target) but for some reason its not working. The part which I don't understand is this image , judging by it the console it's outputting a kernel panic of a Linux boot sequence on the target. This means that you are booting from the SDcard on which you have a embedded
  5. I must have missed a post, but how did you get from a simple helloworld in bare-metal to booting Linux on the Zedboard? The crash you sent us in this post is, as far as I can see, a kernel panic from a Linux boot on the Zedboard, write_led 0xff is also a application in Linux developed by Avnet. Are you trying to run helloworld on a target which has Linux on it? Do you want to use the FMC Pcam while running Linux on the Zedboard? -Ciprian
  6. What serial console are you using? What are the settings? As far as I know the Zedboard has a cypress USB-UART convertor which means it's not ttyUSB1 which will communicate on the UART but the ttyACM0 or ttyACM1... -Ciprian
  7. Hi @erikS, There could be one of two issues you are facing: When installing Vivado on Windows it will automatically install the Digilent drivers when you are done with the installation. On Linux the drivers require sudo permissions which you don't have while installing Vivado. What you need to do is install them separately. The script for the drivers can be found here: <install_location>/Xilinx/Vivado/<version>/data/xicom/cable_drivers/lin64/install_script/install_drivers Make sure that you don't have any board connected and all Vivado related applications are clos
  8. Ciprian

    Zybo z7 evaluation

    This is more of a FPGA size question then a board specific question. We have other boards with the same FPGA, Arty Z7 for example. As for your problem, you might be able to generate the required array, depending on the -20 or -10 variant of the Zybo Z7 and depending on the way you write the HDL code. The best I can recommend is build your project in Vivado for the Zybo Z7 and look at the resource consumption and limitations. -Ciprian
  9. Disclaimer: I considered this Thread closed before writing this post, since Dannny has gotten his answer. Normally I would not comment on this thread anymore because it seams to have concluded, but its so rare to find a naturally developing "philosophical" dilemma in engineering circles that it's hard not to comment on it. I'd also would like to point out that this might help @Dannny in his current and future projects. The way I see it, the dilemma is similar to building a carriage. Zygot and [email protected] are strong advocates of the build it yourself philosophy, this means build your own whe
  10. Ciprian

    Zybo z7 evaluation

    Hi Pier, I'm a bit confused, where do the signals come from? Do you have two external sources or do you generate them in the FPGA? Similarly, do you want to a analog output of the resulting signal or do you only need the samples? -Ciprian
  11. I respectfully disagree. Firstly, it is very different to go from a HDL design to a fully functional Linux system. Mostly because by doing it this way you lock yourself in a path where you must create everything yourself, ultimately rewarding but highly time consuming. Then there is the fact that, given the final requirements, you want a solution which has Linux driver because writing a DMA or even worse a VDMA driver is a very, very big challenge. The solution to @Dannny problem is a VDMA which has the functionality to use multiple frame buffers in the DDR or other memory devices. F
  12. Hi @danny, Before I can answer your question I need to know if you are planning on using it in an embedded linux or not. The solution might vary depending on this. -Ciprian
  13. HI @Ryu, Unfortunately we are not familiar with building Xillinux-2.0 and therefor I can't really help you to the full extend of what you need, you might be right regarding the frequency, but not the right one. The input frequency is used for generating the internal frequencies of the PS which in turn generates the frequencies of the PL, the HDMI is handled in the PL which means that there might be some issues there. Either way there is a external clock on the board which provides the input frequency for the PS (schematic page 10) which is 33.333 MHz. You should not change the settin
  14. Hi @Victor, @zygot is right, you need to pick and choose what you need to do and what your options are. Besides this he is also right when he says that there are different ways of implementing control in user space for IPs. I have suggested UIO because this is the way we do it, and as far as I've seen Xilinx has some examples with it as well. You will most probably not find anything more detailed, in one document, which will explain everything you need to know. You need to take in to account that petalinux is a tool which simplifies an embedded linux build process (which has a l
  15. Hi @Victor, Your question is more of a general Linux programming question than a particular Petalinux one. Like zygot mentioned, it's better to use the drivers when there are drivers to be used. If you have a custom IP or one that dose not have a driver, UIO is your friend. GPIOs are simple enough for them to have one and generally have it loaded (petalinux does that automatically when it finds a GPIO in the imported .hdf). Here is a simple example of how to write a C code using the driver and how it interconnects: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842398
  16. Hi @ zygot We have taken your remarks in to advice and are slowly implementing the requested changes. We'll be adding detailed commentary for changes that make sens (IP changes, SW code changes, etc.) for minor changes such as documentation updates, code commentary fixes, etc. we probably will not. This won't happen all at once but measures are being set up to ensure an easier overview from git commits over the implemented project updates. Regarding testbenches. Its a very good idea and we have started work on some of them, we have not yet reached a final conclusion on how, what and
  17. Hi @xyz, @den_ya, It's an interesting issue you are having and unfortunately there might be a series of reason for which this is happening. Lets start by first knowing exactly what you have. 1. Do you have the resource materials as well as the Workbook or only the Workbook? 2. What version of Vivado are you using? 3. In your final version of the project (with the HLS IP) do you have the control interface active (ap_ctl)? If yes then make sure that the ap_start and the rst_n pins are connected to a const 1 signal. Once I know these answers I can provide more help -
  18. Actually, there is a way of recreating the Vivado project from which the .hdf is obtained. You can do this by using the digilent-vivado-scripts inside the Eclypse-Z7-HW repo. This approach requires you to have the Eclypse Z7 board file, otherwise it will fail. You can use it with both python and from within Vivado... the README.md inside will provide all the information you need. -Ciprian
  19. @zygot Than you for pointing out this issue, there seams to be something we missed either in the git repo or failed to mention in our documentation. In order for easier version control for Xilinx IPs and to simplify some of our more complex IP system, the Zmod IPs are an example for this, we have been using the vivado-hierarchies which work with our IP repo and the Vivado IPs. If you use it to import any Zmod into you block design in Vivado it will create the same hierarchical block as in the example project. For more details on how to use it please visit here. Unfortunately the nature of
  20. Hi @zygot, Thank you for your mostly positive feedback, its nice to see that one of or most active forum members likes the product. While true that we have focused our documentation and subsequently our attention towards the Linux aspect of the project, we have not neglected the desire (or potential desire) of our customers to do just use bare-metal applications and use the 'normal ' Xilinx flow. We tried to keep it as backwards compatible as possible, regarding our usual way of providing demos, while adding a new infrastructure for an OS application. In this sens we had to create t
  21. Hi @cwerner77, I tried to reproduce the problem but unfortunately I could not. You are right though in your assumption, it most likely is a DMA related problem, it expects to receive a certain amount of samples and if the stream is interrupted for some reasons it will stop. If you can record the first time and play back as well then it's most likely not an Audio codec issue. The most likely problem is that the DMA is either in an error state or the IP is no responding to the DMA request. There is a bug in the Demo that if you reprogram the FPGA without resting the board the DMA will
  22. Hi @youngpark, Well I don't know for sure why its not working for you but I would recommend a different approach. The most important thing for you is to make sure that the clock gets propagated throug the design using the clock path and this is done using an ODDR primitive. Therefore I suggest using this aproch: The clock forwarder can be found on our github in the vivado-library. You will also have to constrain it. For this please take a look in the ug903 provided by Xilinx specifically starting page 31. Good Luck -Ciprian
  23. Hi @Himani, Unfortunately I don't know how I can help you, the lab has not been written by us and there could be lots of things missing or even depreciated in the design. Also it might be just detail you have missed... without further knowledge about the project itself (both Vivado and SDK) I can't help you further. -Ciprian
  24. Hi @Himani, unfortunately I'm unfamiliar with the tutorial you are referring to, could you please tell me where I could find it and why you decided to use that particular tutorial? -Ciprian
  25. Hi @SpainFPGAGuy, That is normal, if you ground the rest and measure the voltage on the desired channel you will see that it works ok. -Ciprian