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Ciprian last won the day on December 22 2019

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  1. Hi @cwerner77, I tried to reproduce the problem but unfortunately I could not. You are right though in your assumption, it most likely is a DMA related problem, it expects to receive a certain amount of samples and if the stream is interrupted for some reasons it will stop. If you can record the first time and play back as well then it's most likely not an Audio codec issue. The most likely problem is that the DMA is either in an error state or the IP is no responding to the DMA request. There is a bug in the Demo that if you reprogram the FPGA without resting the board the DMA will hang. Either way I would recommend trying to reset the DMA controller before every playback or record. This would narrow down the search for why it does not work. This can be done with the XAxiDma_Reset() function. I'm also assuming at this point that you did not change anything in the Vivado project or the SDK sources. If you did please let me know, it is unlikely but it might effect the demo. - Ciprian
  2. Hi @youngpark, Well I don't know for sure why its not working for you but I would recommend a different approach. The most important thing for you is to make sure that the clock gets propagated throug the design using the clock path and this is done using an ODDR primitive. Therefore I suggest using this aproch: The clock forwarder can be found on our github in the vivado-library. You will also have to constrain it. For this please take a look in the ug903 provided by Xilinx specifically starting page 31. Good Luck -Ciprian
  3. Hi @Himani, Unfortunately I don't know how I can help you, the lab has not been written by us and there could be lots of things missing or even depreciated in the design. Also it might be just detail you have missed... without further knowledge about the project itself (both Vivado and SDK) I can't help you further. -Ciprian
  4. Hi @Himani, unfortunately I'm unfamiliar with the tutorial you are referring to, could you please tell me where I could find it and why you decided to use that particular tutorial? -Ciprian
  5. Hi @SpainFPGAGuy, That is normal, if you ground the rest and measure the voltage on the desired channel you will see that it works ok. -Ciprian
  6. Hi @SpainFPGAGuy, Sorry for the late response, could you please load the attached .bit file using SD or USB? It will display on the UART port (baud 9600 8N1) the value read at vaux2/3/10/11. Please let me know if this works for you. - Ciprian PS. If it works, contains an example project created in Vivado 2019.1 download.bit
  7. Hi @V94, I'm unsure how you have manged to get a bit stream with the MIPI_CSI_2 IP core force upgrade. The core needs to be updated to the 2019.1 by us first; there are some primitives which have changed. This means that it should fail at synthesis in 2019.1. Unfortunately I cannot give you an estimate when we will be able to update it to the latest version. -Ciprian
  8. As far as I can tell from your code, you are continuously reinitialize and reconfigure the XSysMon (the XADC driver). During this process, which is redundant, you are loosing a lot of samples. Try this instead: #include <stdio.h> #include "xparameters.h" #include "platform.h" #include "xsysmon.h" #include "xil_printf.h" #include "xstatus.h" #include "xuartlite.h" #define UARTLITE_DEVICE_ID XPAR_UARTLITE_0_DEVICE_ID #define SYSMON_DEVICE_ID XPAR_SYSMON_0_DEVICE_ID #define UART_BUFFER_SIZE 16 #define NUMBER_OF_SAMPLES 4500 int main() { static XSysMon SysMonInst; /* System Monitor driver instance */ unsigned int ReceivedCount = 0; unsigned char RecvBuffer[UART_BUFFER_SIZE]; XUartLite UartLite; unsigned int channel = 3; int Status; XSysMon_Config *ConfigPtr; XSysMon *SysMonInstPtr = &SysMonInst; int *sample; //External memory address to store samples sample=(int *)0x60000000; init_platform(); Status = XUartLite_Initialize(&UartLite, UARTLITE_DEVICE_ID); ReceivedCount = 0; while(ReceivedCount==0){ ReceivedCount = XUartLite_Recv(&UartLite, (unsigned char *) RecvBuffer, 1); } ConfigPtr = XSysMon_LookupConfig(SYSMON_DEVICE_ID); if (ConfigPtr == NULL) { return XST_FAILURE; } XSysMon_CfgInitialize(SysMonInstPtr, ConfigPtr, ConfigPtr->BaseAddress); XSysMon_SetAvg(SysMonInstPtr, XSM_AVG_0_SAMPLES); XSysMon_SetAdcClkDivisor(SysMonInstPtr, 39); XSysMon_SetSequencerMode(SysMonInstPtr, XSM_SEQ_MODE_SINGCHAN); XSysMon_SetCalibEnables(SysMonInstPtr, XSM_CFR1_CAL_PS_GAIN_OFFSET_MASK | XSM_CFR1_CAL_ADC_GAIN_OFFSET_MASK); Status= XSysMon_SetSingleChParams(SysMonInstPtr, XSM_CH_AUX_MIN+channel, FALSE, FALSE, TRUE); if(Status != XST_SUCCESS) { return XST_FAILURE; } /* * Disable all the alarms in the Configuration Register 1. */ XSysMon_SetAlarmEnables(SysMonInstPtr, 0x0); while(1){ /* * Wait till the End of conversion */ //print("Capturing\n\r"); for(int i=0;i<NUMBER_OF_SAMPLES;i++){ XSysMon_GetStatus(SysMonInstPtr); /* Clear the old status */ while ((XSysMon_GetStatus(SysMonInstPtr) & XSM_SR_EOC_MASK) != XSM_SR_EOC_MASK); //Four last bits are noise *(sample+i) = XSysMon_GetAdcData(SysMonInstPtr, XSM_CH_AUX_MIN+channel); } //print("Finish capture\n\r"); //xil_printf("samples=np.array(["); for(int i=0;i<NUMBER_OF_SAMPLES-1;i++){ xil_printf("%d,",*(sample+i)); } xil_printf("%d\r\n",*(sample+NUMBER_OF_SAMPLES-1)); xil_printf("end\n"); } cleanup_platform(); return 0; }
  9. @HeroGian Your question is somewhat tricky. It is doable on an ARM but as far as I can gather it's not dynamic, you either start without caches and then everything moves slower or you continue using caches. The dynamical approach is somewhat tricky because you risk freezing your OS. I you want to try that you can find more info here: There might be a better way to do it. What you actually want is just a hardware accelerated memcpy in the DDR, you could try to handle this like an DMA transfer in to DDR from the PL and use a coherency function for it. These are kernel space specific functions so I guess you will have to wirte a kernel driver for it. I strongly suggest reading about continuous memory (CMA) and coherent data transfers + the ACP port of the Zynq before proceeding. Here is a link which might give you an insight in to what and why I suggest this. Although you are using a Zynq, there might be some useful information in the ZynqMP wiki by xilinx about what you need. Sorry for not being able to give you a more coherent and straight forward answer, what you are attempting is tricky. Good Luck, -Ciprian
  10. Ciprian

    PCAM OV5640 Power

    Hi @Sduru, These are BSP errors you will have to regenerate the bsp. Just right click on it in the project explorer (on the left of the main SDK windows) and hit Re-generate BSP sources. These are common xilinx SDK errors, not specific to this project. -Ciprian
  11. Hi @daeroro, #define SPI_DEV "/dev/spidev32766.0" Judging by the .dtsi this should be something else... probably something like spidev1.0. You will need to change to the right device name. To determine which is the right name please run ls /dev/ | grep spi on the running petalinux target. -Ciprian
  12. @ahmedengr.bilal Sorry I have no experience with that, you will need to look it up. -Ciprian
  13. Ciprian

    PCAM OV5640 Power

    Hi @Sduru, In order to see data transfers on the AXI-Stream interface which is connected to the PCAM you will need to configure the PCAM and enable the DMA transfers to do so. This is accomplished using the SDK, therefor you will need to program and monitor the ILA as well as run the SDK program to see any changes on the ILA. I'm guessing that you have a problem with running the code which would explain why you don't see the menu on the console or any traffic on the ILA. I'm guessing that your terminal is set up properly (although using COM1 is unusual), because you mentioned that you ran a hello world project and it displayed the message on the terminal, which leaves us with the possibility that you either have an error running the code in SDK or that there is a bug which does not allow you to get to the menu part of the PCAM code. To test this please put a xil_printf("hello world\n"); at the beginning of the main function and check if it is displayed. -Ciprian
  14. Hi @ahmedengr.bilal, Like I mentioned in the previous post there is no HDMI output from the Linux side, neither the embedded rootFS provided by petalinux nor the kernel configuration we give out is set to accommodate this feature. Regarding the missing media-ctl and v4l2-ctl, you have not activated the v4l-utils in the rootfs configuration of the petalinux. to do this you need to navigate to your petalinux project folder and run: petalinux-config -c rootfs Once the menu appears you need to go to Filesystem Packages->misc->v4l-utils and activate: v4l-utils, libv4l, media-ctl. Rebuild the whole project and it should be working now. -Ciprian
  15. HI @osmaan_khan, To clarify on xillybus and XADC, we have never configured the design which they provide, therefore we don't know how to add the XADC IP to it and interface it with their linux kerne and rootfs. Regarding the VCC and the GND pins, the PMOD connector JA can be configured as XADC or can be used as a simple PMOD connector (following the PMOD standard you need VCC and GND), when using it in a XADC configuration the VCC and the GND can be ignored. All the information on how the XADC works, configurations and limitations can be found in ug480 form xilinx. For instance, you cannot measure a voltage grater 1V using the XADC, you will have to scale your voltage in order to measure it with the XADC (maybe use a voltage divider, it depends on you circuit). The XADC is a Xilinx IP which is configurable both from the IP configuration window in Vivado and trough some registers using the AXI-Lite interface, with a xilinx kernel you should have access to it if the XADC driver is active in the kernel and if the .dts is configured to include the IP. We cannot help you with this, unfortunately; you will have to ask the support team from xillybus about how to manage this. - Ciprian