richilarro

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About richilarro

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  1. Thank you Sergiu for all the info. I may be confused but I could not find a single reference to TX-RX /uart/etc, on the XDC file. On the schematic it shows the pins MIO 48 and 49, which are unaccessible. If I just naively add: set_property PACKAGE_PIN B12 [get_ports {tx}] set_property IOSTANDARD LVCMOS18 [get_ports {tx}] I get the error message: [Vivado 12-1411] Cannot set LOC property of ports, Site location is not valid ["D:/Users/richi/ZYBO/uart/uart.srcs/constrs_1/new/zybo_uart1.xdc":416] Probably, since the UART 1 is coupled to the PS I should build an IP block first, but I was not able to find this instance (UART) within the demo project you linked. Maybe it is indeed a problem still beyond my limited knowledge. I will try to learn a bit more and then re-read this. :-) Thank you anyway. Best regards, Miguel
  2. Hi, sorry if I'm making a very basic question; I want to use a uart protocol to send data to-from a PC, using the j11 USB/UART-JTAG connector on a Zybo Zynq7000. Simply put, my problem is that I don't know where to map the tx/rx wires. In other boards it is clear which pins I should use. In the zynq-7000, the Zybo-Master.xdc file does not have these (only clock, PMODs, leds, switches and buttons). From the zybo Reference manual (page 12), MIO48 and MIO48 are the 1.8V tx-rx pins that receive the serial data converted from the USB packets through the FT2232HQ USB-UART bridge. The problem is that I cannot access those pins. My source is a simple, generic UART code in verilog. I'm using VIVADO. I've tried to create a Block design, enabling the UART1 on the ZYNQ7 Processing System and exporting the xdc file, but apparently it is forbidden to place any wire on the C12 and B12 sites (the physical pins for the MIO 48&49, if I understood correctly. Essentially what I need is a tutorial to create a project in verilog to communicate via the serial port available at the USB bridge. Thanks for any help, Miguel