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  1. Hello, How to generate a variable duty cycle from this code? This code is for 10% duty cycle, 500 Hz frequency, but I want to generate 10%, 30%, 50%, 70% and 90% duty cycle. The clock frequency is 50 MHz. I want to generate a variable duty cycle from 5 variable frequency which are 500 Hz, 1 kHz, 50 kHz, 500 kHz, and 1 MHz. Please someone help me. I need your help. Thank you. DutyCycle(500Hz-10%).vhd DutyCycle500Hz_tb.vhd
  2. Jaiko007

    3 bit output

    Hello, I need to design 3 bit output, which are 000, 001, 010, 011, 100 using FPGA. I'm using VHDL language. I have already designed it. But, the problem is I can't get that desired output I want. I got 000, 001, 011 and 111 outputs. Here I attach my code and testbench and also Isim simulator waveform part. Thank you. selectsig.vhd selectsig_tb.vhd simulator.wcfg
  3. Jaiko007

    8x1 multiplexer

    Hello, I want to design 8x1 multiplexer using FPGA. But, I just only have 5 options of input, which are freq1, freq2, freq3, freq4, and freq5. Is it possible to design it with only just have 5 options of input? If possible, how doing it? I'm using Xilinx and the language I used is VHDL. Here I attach a picture. Please help me. Thank you.
  4. Jaiko007

    MUX 2x1 using VHDL

    Hello, I need to design PWM for a multiplexer 2x1 for my project. The description is: If select = 0, output = input 1 (10kHz) If select = 1, output = input 2 (100kHz) The problem is, I don't know how to implement that frequency in my coding. Is it possible to do that. If yes, how making it? Someone please help me. Here, I attach my code. mux2to1.vhd mux2to1_tb.vhd Thank you.
  5. Hello, I need to design frequency divider from 50MHz to 200Hz using FPGA. I'm using Xilinx and the language that I used is VHDL language. I got stuck because I can't get the output. So, anyone can help me? This is for the code,FreqDivider.vhd and this is for testbench, FreqDivider_tb.vhd. Thanks.