I've got a HDMI link set up between two Zybos using Digilent's DVI cores (rgb2dvi and dvi2rgb). Having tested everything successfully using a 1080p pipeline, however upon switching to VGA resolutions (640x480) the sink part cannot successfully decode the stream. It never occurred to me that low resolutions would pose an issue - but I've been banging my head on a wall with this one!
As per the documentation, I've adjusted some constraints and multiplier / divider combinations for the MMCM in the dvi2rgb core and the clock recovery block is successfully recovering my 25.175 MHz pixel clock (although interestingly it is somehow still able to recover it when the MMCM is configured for 1080p - something I wasn't expecting as the VCO is operating way out of spec at 125 MHz). I'm not getting any activity on the pVDE or CTRL signals, so I think there's something up with the phase alignment or channel bonding.
Receiver block diagram is attached, but it's pretty standard.
I've just noticed that the documentation lists the lower limit for the pixel clock as 40 MHz. Initially I thought this was due to the VCO range, but I also just noticed that the 32-tap delay spans 2.5ns, which happens to be the period of a single bit at 40 Hz. Is my limitation down to the deskew implementation?