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  1. Like
    Shruthi reacted to JColvin in 'SIM_MONITOR_FILE' placement   
    Hi Shruthi,
    I have asked some of our applications engineers about this; they will get back to you here on the forum.
  2. Like
    Shruthi reacted to hamster in Basys3. How to interface Analog Sensor and Servo motor?   
    Hi Shruthi,
    1) check page 60 - table 4-4. The channel numbering is a little bit odd.
    2) Not sure,  as XADC is only available on 7-Series FPGAs. I guess it is for future chips, and I guess it only matters for simulation.
    3) If you want to only read channel 6, yes. See figure 3-1 on page 36. 
  3. Like
    Shruthi reacted to sLowe in How to create an analog stimulus file for use with Xilinx XADC ('SIM_MONITOR_FILE') for Artix7 board?   
    Hey Shruthi,
    I believe the correct way to do this is by making a .txt or .csv file and then loading that into the XADC IP block under ANALOG Sim File Options on the basic tab. The formatting of these files is discussed on page 41-43 of the product guide linked below.
    I've never done this before but if you run into any walls post here again and we can help you figure this out!
  4. Like
    Shruthi reacted to hamster in Basys3. How to interface Analog Sensor and Servo motor?   
    Hi Arvy,
    Here is some code I wrote tonight. It includes the XADC instance, set to measure channel 6 in unipolar mode.

    library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.NUMERIC_STD.ALL; Library UNISIM; use UNISIM.vcomponents.all; entity xadc_test is     Port ( clk100   : in  STD_LOGIC;            led   : out STD_LOGIC_VECTOR (15 downto 0);            JXADC : in  STD_LOGIC_VECTOR (7 downto 0)); end xadc_test; architecture Behavioral of xadc_test is     signal reading : std_logic_vector(15 downto 0) := (others => '0');     signal muxaddr : std_logic_vector( 4 downto 0) := (others => '0');     signal channel : std_logic_vector( 4 downto 0) := (others => '0');     signal vauxn   : std_logic_vector(15 downto 0) := (others => '0');     signal vauxp   : std_logic_vector(15 downto 0) := (others => '0'); begin     led <= reading;     -----------------------------------     -- Pass through the analogue inputs     -----------------------------------     vauxp(6)  <= jxadc(0);  vauxn(6)  <= jxadc(4);     vauxp(14) <= jxadc(1);  vauxn(14) <= jxadc(5);     vauxp(7)  <= jxadc(2);  vauxn(7)  <= jxadc(6);     vauxp(15) <= jxadc(3);  vauxn(15) <= jxadc(7);       XADC_inst : XADC generic map (       -- INIT_40 - INIT_42: XADC configuration registers       INIT_40 => X"9000", -- averaging of 16 selected for external channels       INIT_41 => X"2ef0", -- Continuous Seq Mode, Disable unused ALMs, Enable calibration       INIT_42 => X"0800", -- ACLK = DCLK/8 = 100MHz / 8 = 12.5 MHz        -- INIT_48 - INIT_4F: Sequence Registers       INIT_48 => X"4701", -- CHSEL1 - enable Temp VCCINT, VCCAUX, VCCBRAM, and calibration       INIT_49 => X"000CC", -- CHSEL2 - enable aux analog channels 6,7,14,15       INIT_4A => X"0000", -- SEQAVG1 disabled all channels       INIT_4B => X"0000", -- SEQAVG2 disabled all channels       INIT_4C => X"0000", -- SEQINMODE0 - all channels unipolar       INIT_4D => X"00CC", -- SEQINMODE1 - all channels unipolar       INIT_4E => X"0000", -- SEQACQ0 - No extra settling time all channels       INIT_4F => X"0000", -- SEQACQ1 - No extra settling time all channels       -- INIT_50 - INIT_58, INIT5C: Alarm Limit Registers       INIT_50 => X"b5ed", -- Temp upper alarm trigger 85°C       INIT_51 => X"5999", -- Vccint upper alarm limit 1.05V       INIT_52 => X"A147", -- Vccaux upper alarm limit 1.89V       INIT_53 => X"dddd", -- OT upper alarm limit 125°C - see Thermal Management       INIT_54 => X"a93a", -- Temp lower alarm reset 60°C       INIT_55 => X"5111", -- Vccint lower alarm limit 0.95V       INIT_56 => X"91Eb", -- Vccaux lower alarm limit 1.71V       INIT_57 => X"ae4e", -- OT lower alarm reset 70°C - see Thermal Management       INIT_58 => X"5999", -- VCCBRAM upper alarm limit 1.05V       INIT_5C => X"5111", -- VCCBRAM lower alarm limit 0.95V       -- Simulation attributes: Set for proper simulation behavior       SIM_DEVICE       => "7SERIES",    -- Select target device (values)       SIM_MONITOR_FILE => "design.txt"  -- Analog simulation data file name    ) port map (       -- ALARMS: 8-bit (each) output: ALM, OT       ALM          => open,             -- 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram       OT           => open,             -- 1-bit output: Over-Temperature alarm       -- STATUS: 1-bit (each) output: XADC status ports       BUSY         => open,             -- 1-bit output: ADC busy output       CHANNEL      => channel,          -- 5-bit output: Channel selection outputs       EOC          => open,             -- 1-bit output: End of Conversion       EOS          => open,             -- 1-bit output: End of Sequence       JTAGBUSY     => open,             -- 1-bit output: JTAG DRP transaction in progress output       JTAGLOCKED   => open,             -- 1-bit output: JTAG requested DRP port lock       JTAGMODIFIED => open,             -- 1-bit output: JTAG Write to the DRP has occurred       MUXADDR      => muxaddr,          -- 5-bit output: External MUX channel decode              -- Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0]       VAUXN        => vauxn,            -- 16-bit input: N-side auxiliary analog input       VAUXP        => vauxp,            -- 16-bit input: P-side auxiliary analog input              -- CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs       CONVST       => '0',              -- 1-bit input: Convert start input       CONVSTCLK    => '0',              -- 1-bit input: Convert start input       RESET        => '0',              -- 1-bit input: Active-high reset              -- Dedicated Analog Input Pair: 1-bit (each) input: VP/VN       VN           => '0', -- 1-bit input: N-side analog input       VP           => '0', -- 1-bit input: P-side analog input              -- Dynamic Reconfiguration Port (DRP) -- hard set to read channel 6 (XADC4/XADC0)       DO           => reading,       DRDY         => open,       DADDR        => "0010110",  -- The address for reading AUX channel 6       DCLK         => clk100,       DEN          => '1',       DI           => (others => '0'),       DWE          => '0'    ); end Behavioral; And here is the XDC file for the Basys3: set_property PACKAGE_PIN W5 [get_ports clk100]                                 set_property IOSTANDARD LVCMOS33 [get_ports clk100]     create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk100] ## LEDs set_property PACKAGE_PIN U16 [get_ports {led[0]}]                         set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}] set_property PACKAGE_PIN E19 [get_ports {led[1]}]                         set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}] set_property PACKAGE_PIN U19 [get_ports {led[2]}]                         set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}] set_property PACKAGE_PIN V19 [get_ports {led[3]}]                         set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}] set_property PACKAGE_PIN W18 [get_ports {led[4]}]                         set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}] set_property PACKAGE_PIN U15 [get_ports {led[5]}]                         set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}] set_property PACKAGE_PIN U14 [get_ports {led[6]}]                         set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}] set_property PACKAGE_PIN V14 [get_ports {led[7]}]                         set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}] set_property PACKAGE_PIN V13 [get_ports {led[8]}]                         set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}] set_property PACKAGE_PIN V3 [get_ports {led[9]}]                         set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}] set_property PACKAGE_PIN W3 [get_ports {led[10]}]                         set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}] set_property PACKAGE_PIN U3 [get_ports {led[11]}]                         set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}] set_property PACKAGE_PIN P3 [get_ports {led[12]}]                         set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}] set_property PACKAGE_PIN N3 [get_ports {led[13]}]                         set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}] set_property PACKAGE_PIN P1 [get_ports {led[14]}]                         set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}] set_property PACKAGE_PIN L1 [get_ports {led[15]}]                         set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}] ##Pmod Header JXADC ##Sch name = XA1_P set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]                     set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}] ##Sch name = XA2_P set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]                     set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}] ##Sch name = XA3_P set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]                     set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}] ##Sch name = XA4_P set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]                     set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}] ##Sch name = XA1_N set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]                     set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}] ##Sch name = XA2_N set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]                     set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}] ##Sch name = XA3_N set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]                     set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}] ##Sch name = XA4_N set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]                     set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}] When downloaded to your board, the value displayed in binary on the the LEDs should reflect the voltage on Pin 0 if the PXADC. I tested just by pushing some header pins into the PMOD and touching the pin - not exactly a complete test, but enough to show that it does something.
    NOTE: THE FULL SCALE VOLTAGE FOR THE XADC IS 1V, so some crafty planning might be required to interface to it.
  5. Like
    Shruthi reacted to JColvin in Can I use XADC to sample the input signals?   
    Hi Shruthi,
    I'm not sure if anybody at Digilent has done much with the HDL Coder from Matlab, but after doing a bit of research on my own, it seems you can either use the HDL Coder within Xilinx tools (for which you would need the Vivado System Generator), or if you have already generated the Verilog code, you could just use the normal Vivado Design Suite to implement your code onto the FPGA. So yes, I think you can just use the Vivado Design Suite and XADC.
    Again, I personally haven't used the HDL Coder, so more detailed questions would need to be addressed to MathWorks.