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Posts posted by Shruthi

  1. Hello all,


    I'm trying to use XADC aux channel-6 outputs as input to my unit under test. The CFBLMS module has input parameters for every change in the MEASURED_AUX6 voltage. 


    Can you help me how to do that? Below is the code, and bolded is the part where I wish to take every change in the value of MEASURED_AUX6 as a separate input parameter.


    `timescale 1ns/1ps

    module ug480_tb;
    reg [3:0] VAUXP, VAUXN;
    reg VP, VN;
    reg RESET;
    reg DCLK;

    wire [15:0] MEASURED_AUX14, MEASURED_AUX15;
    wire [7:0] ALM;
    wire OT;
    wire EOC;
    wire EOS;
    wire [4:0] CHANNEL;

    DCLK = 0;
    RESET = 0;

    always #(10) DCLK= ~DCLK;

    // Instantiate the Unit Under Test (UUT)
    ug480 uut (
    .ALM (ALM),
    .DCLK (DCLK),


    integer i [0:4];

    wire [15:0] e [0:3]
    reg [15:0] x [0:3];
    initial begin
    for (i=0; i<4; i=i+1)
    x = MEASURED_AUX6;


    CFBLMS uut (.x_00(x[0]), .x_01(x[1]), .x_02(x[2]), .x_03(x[3]), .e0(e[0]), .e1(e[1]), .e2(e[2]), .e3(e[3]));


    Thank you,

    Shruthi Sampathkumar.

  2. Hello all,

    I'm trying to simulate LMS algorithm with digital samples from XADC out of Auxillary channel 6.

    In my step to update weight, I don't understand how to bring about weight update. It reads Weight_in and Weight_out as XXXX.


    Please check the bolded. area in LMS_weight module.



    module LMShruthi ( DCLK, RESET, Desired_in, mux ); 
    input DCLK, RESET;
    input   signed [15:0] Desired_in; 
    output signed [15:0] mux; 
    wire [15:0] mu; //mu=0.0000001
    reg signed [15:0] Data_in; 
    wire signed [15:0] e;
    wire signed [31:0] Product_32, y; 
    assign mu  = 16'b0000000001100110;   
    always # (50000) Data_in = Desired_in;
    assign Product_32 = mu * Data_in; 
        assign mux = Product_32[24:9];
    LMS_weight uut3   ( .DCLK(DCLK), .RESET(RESET), .Data_in(Data_in), .mux(mux), .y(y) ); 
        assign e = Desired_in - y[24:9];  
    module LMS_weight (DCLK, RESET, Data_in, mux, y); 
        input DCLK,RESET;
        input signed [15:0] Data_in,mux; 
        output  signed [31:0] y; 
        wire signed [15:0] Weight_in;
        wire signed [15:0] Weight_out, emux; 
        wire signed [31:0] Product_32; 
        assign Product_32 = Data_in * mux; 
        assign emux = Product_32[26:11]; 
        assign Weight_in = (RESET==1'b1) ? 16'h0000 : (emux + Weight_out);
        assign y = Weight_out * Data_in; 

    Thank you,

    Shruthi Sampathkumar.

  3. Hi, 

    I am trying to use Vivado 2015.4's XADC in my design using Basys3 (xc7a35tcpg236-1). I do not know where to place my SIM_MONITOR_FILE (design.txt) so that the design reads it during simulation. 

    Thank you,


  4. On November 30, 2015 at 1:59 AM, hamster said:

    Hi Arvy,

    Here is some code I wrote tonight. It includes the XADC instance, set to measure channel 6 in unipolar mode.



    library IEEE;
    use IEEE.STD_LOGIC_1164.ALL;
    Library UNISIM;
    use UNISIM.vcomponents.all;
    entity xadc_test is
        Port ( clk100   : in  STD_LOGIC;
               led   : out STD_LOGIC_VECTOR (15 downto 0);
               JXADC : in  STD_LOGIC_VECTOR (7 downto 0));
    end xadc_test;
    architecture Behavioral of xadc_test is
        signal reading : std_logic_vector(15 downto 0) := (others => '0');
        signal muxaddr : std_logic_vector( 4 downto 0) := (others => '0');
        signal channel : std_logic_vector( 4 downto 0) := (others => '0');
        signal vauxn   : std_logic_vector(15 downto 0) := (others => '0');
        signal vauxp   : std_logic_vector(15 downto 0) := (others => '0');
        led <= reading;
        -- Pass through the analogue inputs
        vauxp(6)  <= jxadc(0);  vauxn(6)  <= jxadc(4);
        vauxp(14) <= jxadc(1);  vauxn(14) <= jxadc(5);
        vauxp(7)  <= jxadc(2);  vauxn(7)  <= jxadc(6);
        vauxp(15) <= jxadc(3);  vauxn(15) <= jxadc(7);
    XADC_inst : XADC generic map (
          -- INIT_40 - INIT_42: XADC configuration registers
          INIT_40 => X"9000", -- averaging of 16 selected for external channels
          INIT_41 => X"2ef0", -- Continuous Seq Mode, Disable unused ALMs, Enable calibration
          INIT_42 => X"0800", -- ACLK = DCLK/8 = 100MHz / 8 = 12.5 MHz 
          -- INIT_48 - INIT_4F: Sequence Registers
          INIT_48 => X"4701", -- CHSEL1 - enable Temp VCCINT, VCCAUX, VCCBRAM, and calibration
          INIT_49 => X"000CC", -- CHSEL2 - enable aux analog channels 6,7,14,15
          INIT_4A => X"0000", -- SEQAVG1 disabled all channels
          INIT_4B => X"0000", -- SEQAVG2 disabled all channels
          INIT_4C => X"0000", -- SEQINMODE0 - all channels unipolar
          INIT_4D => X"00CC", -- SEQINMODE1 - all channels unipolar
          INIT_4E => X"0000", -- SEQACQ0 - No extra settling time all channels
          INIT_4F => X"0000", -- SEQACQ1 - No extra settling time all channels
          -- INIT_50 - INIT_58, INIT5C: Alarm Limit Registers
          INIT_50 => X"b5ed", -- Temp upper alarm trigger 85°C
          INIT_51 => X"5999", -- Vccint upper alarm limit 1.05V
          INIT_52 => X"A147", -- Vccaux upper alarm limit 1.89V
          INIT_53 => X"dddd", -- OT upper alarm limit 125°C - see Thermal Management
          INIT_54 => X"a93a", -- Temp lower alarm reset 60°C
          INIT_55 => X"5111", -- Vccint lower alarm limit 0.95V
          INIT_56 => X"91Eb", -- Vccaux lower alarm limit 1.71V
          INIT_57 => X"ae4e", -- OT lower alarm reset 70°C - see Thermal Management
          INIT_58 => X"5999", -- VCCBRAM upper alarm limit 1.05V
          INIT_5C => X"5111", -- VCCBRAM lower alarm limit 0.95V
          -- Simulation attributes: Set for proper simulation behavior
          SIM_DEVICE       => "7SERIES",    -- Select target device (values)
          SIM_MONITOR_FILE => "design.txt"  -- Analog simulation data file name
       ) port map (
          -- ALARMS: 8-bit (each) output: ALM, OT
          ALM          => open,             -- 8-bit output: Output alarm for temp, Vccint, Vccaux and Vccbram
          OT           => open,             -- 1-bit output: Over-Temperature alarm
          -- STATUS: 1-bit (each) output: XADC status ports
          BUSY         => open,             -- 1-bit output: ADC busy output
          CHANNEL      => channel,          -- 5-bit output: Channel selection outputs
          EOC          => open,             -- 1-bit output: End of Conversion
          EOS          => open,             -- 1-bit output: End of Sequence
          JTAGBUSY     => open,             -- 1-bit output: JTAG DRP transaction in progress output
          JTAGLOCKED   => open,             -- 1-bit output: JTAG requested DRP port lock
          JTAGMODIFIED => open,             -- 1-bit output: JTAG Write to the DRP has occurred
          MUXADDR      => muxaddr,          -- 5-bit output: External MUX channel decode
          -- Auxiliary Analog-Input Pairs: 16-bit (each) input: VAUXP[15:0], VAUXN[15:0]
          VAUXN        => vauxn,            -- 16-bit input: N-side auxiliary analog input
          VAUXP        => vauxp,            -- 16-bit input: P-side auxiliary analog input
          -- CONTROL and CLOCK: 1-bit (each) input: Reset, conversion start and clock inputs
          CONVST       => '0',              -- 1-bit input: Convert start input
          CONVSTCLK    => '0',              -- 1-bit input: Convert start input
          RESET        => '0',              -- 1-bit input: Active-high reset
          -- Dedicated Analog Input Pair: 1-bit (each) input: VP/VN
          VN           => '0', -- 1-bit input: N-side analog input
          VP           => '0', -- 1-bit input: P-side analog input
          -- Dynamic Reconfiguration Port (DRP) -- hard set to read channel 6 (XADC4/XADC0)
          DO           => reading,
          DRDY         => open,
          DADDR        => "0010110",  -- The address for reading AUX channel 6
          DCLK         => clk100,
          DEN          => '1',
          DI           => (others => '0'),
          DWE          => '0'
    end Behavioral;
    And here is the XDC file for the Basys3:
    set_property PACKAGE_PIN W5 [get_ports clk100]                            
        set_property IOSTANDARD LVCMOS33 [get_ports clk100]
        create_clock -add -name sys_clk_pin -period 10.00 -waveform {0 5} [get_ports clk100]
    ## LEDs
    set_property PACKAGE_PIN U16 [get_ports {led[0]}]                    
        set_property IOSTANDARD LVCMOS33 [get_ports {led[0]}]
    set_property PACKAGE_PIN E19 [get_ports {led[1]}]                    
        set_property IOSTANDARD LVCMOS33 [get_ports {led[1]}]
    set_property PACKAGE_PIN U19 [get_ports {led[2]}]                    
        set_property IOSTANDARD LVCMOS33 [get_ports {led[2]}]
    set_property PACKAGE_PIN V19 [get_ports {led[3]}]                    
        set_property IOSTANDARD LVCMOS33 [get_ports {led[3]}]
    set_property PACKAGE_PIN W18 [get_ports {led[4]}]                    
        set_property IOSTANDARD LVCMOS33 [get_ports {led[4]}]
    set_property PACKAGE_PIN U15 [get_ports {led[5]}]                    
        set_property IOSTANDARD LVCMOS33 [get_ports {led[5]}]
    set_property PACKAGE_PIN U14 [get_ports {led[6]}]                    
        set_property IOSTANDARD LVCMOS33 [get_ports {led[6]}]
    set_property PACKAGE_PIN V14 [get_ports {led[7]}]                    
        set_property IOSTANDARD LVCMOS33 [get_ports {led[7]}]
    set_property PACKAGE_PIN V13 [get_ports {led[8]}]                    
        set_property IOSTANDARD LVCMOS33 [get_ports {led[8]}]
    set_property PACKAGE_PIN V3 [get_ports {led[9]}]                    
        set_property IOSTANDARD LVCMOS33 [get_ports {led[9]}]
    set_property PACKAGE_PIN W3 [get_ports {led[10]}]                    
        set_property IOSTANDARD LVCMOS33 [get_ports {led[10]}]
    set_property PACKAGE_PIN U3 [get_ports {led[11]}]                    
        set_property IOSTANDARD LVCMOS33 [get_ports {led[11]}]
    set_property PACKAGE_PIN P3 [get_ports {led[12]}]                    
        set_property IOSTANDARD LVCMOS33 [get_ports {led[12]}]
    set_property PACKAGE_PIN N3 [get_ports {led[13]}]                    
        set_property IOSTANDARD LVCMOS33 [get_ports {led[13]}]
    set_property PACKAGE_PIN P1 [get_ports {led[14]}]                    
        set_property IOSTANDARD LVCMOS33 [get_ports {led[14]}]
    set_property PACKAGE_PIN L1 [get_ports {led[15]}]                    
        set_property IOSTANDARD LVCMOS33 [get_ports {led[15]}]
    ##Pmod Header JXADC
    ##Sch name = XA1_P
    set_property PACKAGE_PIN J3 [get_ports {JXADC[0]}]                
        set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[0]}]
    ##Sch name = XA2_P
    set_property PACKAGE_PIN L3 [get_ports {JXADC[1]}]                
        set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[1]}]
    ##Sch name = XA3_P
    set_property PACKAGE_PIN M2 [get_ports {JXADC[2]}]                
        set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[2]}]
    ##Sch name = XA4_P
    set_property PACKAGE_PIN N2 [get_ports {JXADC[3]}]                
        set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[3]}]
    ##Sch name = XA1_N
    set_property PACKAGE_PIN K3 [get_ports {JXADC[4]}]                
        set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[4]}]
    ##Sch name = XA2_N
    set_property PACKAGE_PIN M3 [get_ports {JXADC[5]}]                
        set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[5]}]
    ##Sch name = XA3_N
    set_property PACKAGE_PIN M1 [get_ports {JXADC[6]}]                
        set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[6]}]
    ##Sch name = XA4_N
    set_property PACKAGE_PIN N1 [get_ports {JXADC[7]}]                
        set_property IOSTANDARD LVCMOS33 [get_ports {JXADC[7]}]

    When downloaded to your board, the value displayed in binary on the the LEDs should reflect the voltage on Pin 0 if the PXADC. I tested just by pushing some header pins into the PMOD and touching the pin - not exactly a complete test, but enough to show that it does something.

    NOTE: THE FULL SCALE VOLTAGE FOR THE XADC IS 1V, so some crafty planning might be required to interface to it.

    Hi Hamster,

    1. Is it INIT_49 => X"coco", -- for channels 6,7,14,15?

    INIT_49 => X"000CC", -- CHSEL2 - enable aux analog channels 6,7,14,15

    2. I use Basys3 (xc7a35tcpg236-1) board. Is it compulsory to specify the below?

    SIM_DEVICE       => "7SERIES",    -- Select target device (values)

    3. Should I initialize DADDR like this one?

    DADDR        => "0010110",  -- The address for reading AUX channel 6

    Thank you,


  5. I ran speech simulation (analog) on Matlab, and here is the code and result. I want create an analog stimulus file for UNISIM for XADC execution on Xilinx Vivado. I use Vivado 2015.4 with board Artix7 (xc7t35cpg236 - 1C).


    1. How to make an analog stimulus file using these information? I will need Time(ns), VAUXP(V), TEMP, VCCINT, VCCAUX, VCCBRAM values.

    2. How many set of readings can I take?

    3. Should the time be in millisecond, nanoseconds or seconds?


    Please find attached 'SIM_MONITOR_FILE' saved in data.xls and the simulation file for word 'Jam', obtained using Matlab 'audiorecorder'.




  6. I've Verilog code generated from Matlab files using HDL Coder tool for Matlab. It is an adaptive filter design which requires speech signal input, that is to be sampled and given as inputs to my module.


    Do I need to install Vivado System Generator along with its corresponding Matlab configuration to implement a adaptive filter file on a Basys3 board?


    Or just install Vivado Design Suite and use XADC to sample the input signals, and implement it on board?



    Shruthi Sampathkumar.