Shruthi

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  1. Shruthi

    XADC output for module instantiation

    Hello all, I'm trying to use XADC aux channel-6 outputs as input to my unit under test. The CFBLMS module has input parameters for every change in the MEASURED_AUX6 voltage. Can you help me how to do that? Below is the code, and bolded is the part where I wish to take every change in the value of MEASURED_AUX6 as a separate input parameter. `timescale 1ns/1ps module ug480_tb; reg [3:0] VAUXP, VAUXN; reg VP, VN; reg RESET; reg DCLK; wire [15:0] MEASURED_TEMP, MEASURED_VCCINT, MEASURED_VCCAUX; wire [15:0] MEASURED_VCCBRAM, MEASURED_AUX6, MEASURED_AUX7; wire [15:0] MEASURED_AUX14, MEASURED_AUX15; wire [7:0] ALM; wire OT; wire EOC; wire EOS; wire [4:0] CHANNEL; initial begin DCLK = 0; RESET = 0; end always #(10) DCLK= ~DCLK; // Instantiate the Unit Under Test (UUT) ug480 uut ( .VAUXP (VAUXP), .VAUXN (VAUXN), .RESET (RESET), .ALM (ALM), .DCLK (DCLK), .MEASURED_TEMP (MEASURED_TEMP), .MEASURED_VCCINT (MEASURED_VCCINT), .MEASURED_VCCAUX (MEASURED_VCCAUX), .MEASURED_VCCBRAM (MEASURED_VCCBRAM), .MEASURED_AUX6 (MEASURED_AUX6), .MEASURED_AUX7 (MEASURED_AUX7), .MEASURED_AUX14 (MEASURED_AUX14), .MEASURED_AUX15 (MEASURED_AUX15) ); integer i [0:4]; wire [15:0] e [0:3] reg [15:0] x [0:3]; initial begin for (i=0; i<4; i=i+1) begin x = MEASURED_AUX6; end end CFBLMS uut (.x_00(x[0]), .x_01(x[1]), .x_02(x[2]), .x_03(x[3]), .e0(e[0]), .e1(e[1]), .e2(e[2]), .e3(e[3])); endmodule Thank you, Shruthi Sampathkumar.
  2. Hello all, I'm trying to simulate LMS algorithm with digital samples from XADC out of Auxillary channel 6. In my step to update weight, I don't understand how to bring about weight update. It reads Weight_in and Weight_out as XXXX. Please check the bolded. area in LMS_weight module. *********************** module LMShruthi ( DCLK, RESET, Desired_in, mux ); input DCLK, RESET; input signed [15:0] Desired_in; output signed [15:0] mux; wire [15:0] mu; //mu=0.0000001 reg signed [15:0] Data_in; wire signed [15:0] e; wire signed [31:0] Product_32, y; assign mu = 16'b0000000001100110; always # (50000) Data_in = Desired_in; assign Product_32 = mu * Data_in; assign mux = Product_32[24:9]; LMS_weight uut3 ( .DCLK(DCLK), .RESET(RESET), .Data_in(Data_in), .mux(mux), .y(y) ); assign e = Desired_in - y[24:9]; endmodule *********************************************************** module LMS_weight (DCLK, RESET, Data_in, mux, y); input DCLK,RESET; input signed [15:0] Data_in,mux; output signed [31:0] y; wire signed [15:0] Weight_in; wire signed [15:0] Weight_out, emux; wire signed [31:0] Product_32; assign Product_32 = Data_in * mux; assign emux = Product_32[26:11]; assign Weight_in = (RESET==1'b1) ? 16'h0000 : (emux + Weight_out); assign y = Weight_out * Data_in; endmodule *********************************************************** Thank you, Shruthi Sampathkumar.
  3. Shruthi

    'SIM_MONITOR_FILE' placement

    Hi, I am trying to use Vivado 2015.4's XADC in my design using Basys3 (xc7a35tcpg236-1). I do not know where to place my SIM_MONITOR_FILE (design.txt) so that the design reads it during simulation. Thank you, Shruthi
  4. On November 30, 2015 at 1:59 AM, hamster said:

    Hi Hamster,

    Based on "

     "

    1. Is it INIT_49 => X"coco", -- for channels 6,7,14,15?

    INIT_49 => X"000CC", -- CHSEL2 - enable aux analog channels 6,7,14,15

    2. I use Basys3 (xc7a35tcpg236-1) board. Is it compulsory to specify the below?

    SIM_DEVICE       => "7SERIES",    -- Select target device (values)

    3. Should I initialize DADDR like this one?

    DADDR        => "0010110",  -- The address for reading AUX channel 6

    Thank you,

    Shruthi.

  5. Shruthi

    Basys3. How to interface Analog Sensor and Servo motor?

    Hi Hamster, 1. Is it INIT_49 => X"coco", -- for channels 6,7,14,15? INIT_49 => X"000CC", -- CHSEL2 - enable aux analog channels 6,7,14,15 2. I use Basys3 (xc7a35tcpg236-1) board. Is it compulsory to specify the below? SIM_DEVICE => "7SERIES", -- Select target device (values) 3. Should I initialize DADDR like this one? DADDR => "0010110", -- The address for reading AUX channel 6 Thank you, Shruthi.
  6. I ran speech simulation (analog) on Matlab, and here is the code and result. I want create an analog stimulus file for UNISIM for XADC execution on Xilinx Vivado. I use Vivado 2015.4 with board Artix7 (xc7t35cpg236 - 1C). 1. How to make an analog stimulus file using these information? I will need Time(ns), VAUXP(V), TEMP, VCCINT, VCCAUX, VCCBRAM values. 2. How many set of readings can I take? 3. Should the time be in millisecond, nanoseconds or seconds? Please find attached 'SIM_MONITOR_FILE' saved in data.xls and the simulation file for word 'Jam', obtained using Matlab 'audiorecorder'. data.xls
  7. I've Verilog code generated from Matlab files using HDL Coder tool for Matlab. It is an adaptive filter design which requires speech signal input, that is to be sampled and given as inputs to my module. Do I need to install Vivado System Generator along with its corresponding Matlab configuration to implement a adaptive filter file on a Basys3 board? Or just install Vivado Design Suite and use XADC to sample the input signals, and implement it on board? Thanks, Shruthi Sampathkumar.