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About Alex

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  1. What device do you use in the design?
  2. @Arri I find out a tutorial how to program PL of Zynq from Vivado
  3. As far as I remember correctly, you need to program PL through SDK in Zynq
  4. I recommend you to go through the programming guide
  5. Alex

    Looking at Arty S7...

    What do you want to intend to do with high level language? In other word, how do you want to use C in Vivado? Do you want to do high level synthesis ? Or you build the hardware design and use SDK ?
  6. I don’t know whether cursors can be included in the image file. I doubt that you can graph and phase in the same plot with Waveforms. However, you may do that with python or C++. @attila can answer these questions
  7. You may try to us Pmod level shifter
  8. Hi, I recommend you to email this question to the NetFPGA SUME group. They have better idea about the NIC reference design. Since you register their git already. There is community email address. You can send questions to that email address. The community member will help you.
  9. I guess you should install Digilent plug-in.
  10. Have you put the board file in the Vivado folder?
  11. You can try
  12. I assume you mean ISE webpack? If so, you recommend to program Basys 3 with Vivado webpack. I think you might be able to program Basys 3 with ISE webpack with Adept but haven't tried that. Perhaps other memebers can tell you.
  13. I think so. It can decode 16 nit addresses and 8-bit data simultaneously User programmable input and output LVCMOS voltage levels from 1.2V to 3.3V 3) (5V compatible 4) ) You can check details at
  14. Have you used the coax cable ? This link shows how to get the 12MHz