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About ngong

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  1. p.s. if you like to know: I may have found two minor inconsistencies in chapter 10.2 of the tutorial: OK <- Finish, display_hello_world <- Hello_world.
  2. Yes, thank you very much Tommy, JColvin. worked out fine now - can see Hello world in the terminal. Looking forward to build my own peripheral. The reason why it did not work in the first place was different from what we thought: I usually develop on Linux. Unfortunately Xilinx does not distribute for (the famous and widespread, rock solid) Debian Jessy distribution - actually Mint LMDE. That is why I have installed VirtualBox and win7 as a guest. However, the assigned disk is not as large as with a usual desktop. Therefore I used to store anything possible to drive G:\, which is mapped away to the Linux disk. I had no trouble so far with this mapping and I am using this configuration for years now. Trying the new tutorial - which is a lot easier, thank you again - I ran into similar access failure messages as mentioned above. However now got the idea to try on C:\ - which cut the Gordian knot. Kind Reards Rolf
  3. At Step 6.4 of I not only get the expected Critical Message BD 41-1273 but two more and the block do not change (does not get more connections after Run Block Automation): [IP_Flow 19-3460] Validation failed on parameter 'XML_INPUT_FILE(XML_INPUT_FILE)' for Specified PRJ file is not readable 'g:/workspace/vivado-examples/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_3/board.prj' . BD Cell '/mig_7series_0' [BD 41-245] set_property error - Validation failed on parameter 'XML_INPUT_FILE(XML_INPUT_FILE)' for Specified PRJ file is not readable 'g:/workspace/vivado-examples/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_3/board.prj' . BD Cell '/mig_7series_0' Customization errors found on '/mig_7series_0'. Restoring to previous valid configuration. [BD 41-1273] Error running apply_rule TCL procedure: ERROR: [Common 17-39] 'set_property' failed due to earlier errors. ::xilinx.com_bd_rule_mig_7series::apply_rule Line 24 What could be my reason for this different behavior? Why is the file g:/workspace/vivado-examples/Arty_GSMB/Arty_GSMB.srcs/sources_1/bd/design_1/ip/design_1_mig_7series_0_3/board.prj requested and what could be the reason for its absence? Any help welcome Rolf
  4. Hi Graham, thank you for this terrific piece of information. Worked super for me - even though I did not know nothing about Vivado and Verilog. Maybe for a very newbie - like me - it is good to know that the Arty board needs a board_file in Vivado/2015.y/data/boards that has to be copied from Digilent ( Design Resources / Vivado Board Files – Wiki prior to following your nice presentation.