gcp

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About gcp

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  • Birthday 01/06/1987

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    hardware and software architecture

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  1. gcp

    Straight-Through/Crossover Cable Connection

    Hello Ms. Bianca, Thank you for the very informative ideas. Could you please check the photo below if I decode the right connection. Thank you very much. Best regards, Glenn
  2. gcp

    Straight-Through/Crossover Cable Connection

    @Bianca Sorry for my confusing message . We actually using the ublox EVK U-27 which includes the SARA U270 and GNSS receiver. Can you please give some comments/advice on our present setup connection? Thanks a lot. Best regards, Glenn
  3. gcp

    Straight-Through/Crossover Cable Connection

    Thank you. Hope to hear it soon.
  4. Hi,

    Could someone help us. We are trying to interface a ublox SARA U270 EVK as a DCE modem into a pmod zedboard FPGA board as a DTE . We used the Pmod RS232 module just to have a direct conection to the pmod pins of the zedboard. Since, the ublox SARA U270 is a DB9 male type, we used  the Male-Male DB9 cable converter using the straight-through cable connection in order to have a coonection to the Pmod RS232 and then to the pmod pins of the zedboard. Before connecting to the pmod pins in the zedboard, we checked  first the voltage levels of the output pins in the Pmod RS232 when ublox SARA U270 is only in power (zedboard is not yet connected). Upon checking the voltage using the multi meter device, the Rx pin reading is variable from 3V to 4.20V.  Our understanding also in the pmod pins on the zedboard is that the voltage level allowed is only 3.3V. Through these readings, our undertanding is that the 3.3V pin will received the 4.20V from the ublox SARA U270 that will eventually damage to the pmod pin on the zedboard. Do we have a correct understanding on the issues? If not, can somebody enlighten us? 

    Thanks.

     

    Best regards,

    glenn

     

     

  5. Dear FPGA experts, Good day! We want some expert advice of our present hardware setup. The setup is to connect the ublox SARA U270 into the xilinx FPGA board. The connection is from the DB9(RS232) of the Ublox SARA U270 into the pmod pins of the xilinx zedboard. Since it has different voltages, ublox SARA U270 is a 1.8V while the pmod pins of xilinx zedboard is 3.3V, we need to used the RS232 converter and a pmod RS232. In RS232 converter cable, we have in doubt of what to use between straight-through and a crossover cable connection. My understanding in the straight-through cable connection is good for unlike devices while on the crossover connection is good for like devices. Based on the issues aboved, we want some enlightenment advices of the expert in this forum: 1. Is my understanding between straight-through and crossover cable connection is correct? 2. In our hardware set-up, what cable connection should we used to connect between ublox SARA U270 and xilinx FPGA board? Thank you very much. God bless and more power!!! Thanks. Best regards, Glenn
  6. gcp

    Difference between BRAM, DRAm and DMA

    @Piasa Thanks for the immediate response. Is my understanding is correct that BRAM is located in the PL side while the DRAM is located in the PS side? Thanks.
  7. Dear FPGA experts, Good day! Can someone enlighten me the difference between BRAM, DRAM and DMA? And in what specific scenario that each be suited to used? We are using the xilinx zedboard device. Thank you very much. Best regards, Glenn
  8. Dear FPGA experts, Good day! We were trying to interface our ublox neo M8U gps into the pmod Zedboard using the UART connection. We successfully created the hardware design in vivado by using the axi_uartlite IP in routing the TxD and RxD pins of the gps to the PL part of the zedboard (spec. Pmod JB1) and export bitstream in SDk environment. Make some editing of the pre-built code example of axi-uartlite, then finally it runs successfully and we can evaluate the packet that coming out from the gps. Upon checking of the packet results, we noticed that the packet data bytes received each clock time is variable in length and it has a maximum of 16 bytes data only. Our expected total data bytes in each time cycle should be 700 bytes. Our questions that needs an expert advice: 1. Is this a standard characteristic of axi-uartlite that the received data bytes in each cycle is less than 16 bytes? 2. We need to get our expected total data bytes in every cycle, is this possible? How can we do it in a code? 3. How to make our set-up more efficient in terms of time in parsing the data packets? I will include our code and hardware design below for you to check. Thanks and hoping to hear from the experts. Best regards, Glenn /****************************************************************************** * * Copyright (C) 2009 - 2014 Xilinx, Inc. All rights reserved. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal * in the Software without restriction, including without limitation the rights * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell * copies of the Software, and to permit persons to whom the Software is * furnished to do so, subject to the following conditions: * * The above copyright notice and this permission notice shall be included in * all copies or substantial portions of the Software. * * Use of the Software is limited solely to applications: * (a) running on a Xilinx device, or * (b) that interact with a Xilinx device through a bus or interconnect. * * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL * XILINX BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF * OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE * SOFTWARE. * * Except as contained in this notice, the name of the Xilinx shall not be used * in advertising or otherwise to promote the sale, use or other dealings in * this Software without prior written authorization from Xilinx. * ******************************************************************************/ /* * helloworld.c: simple test application * * This application configures UART 16550 to baud rate 9600. * PS7 UART (Zynq) is not initialized by this application, since * bootrom/bsp configures it to baud rate 115200 * * ------------------------------------------------ * | UART TYPE BAUD RATE | * ------------------------------------------------ * uartns550 9600 * uartlite Configurable only in HW design * ps7_uart 115200 (configured by bootrom/bsp) */ #include <stdio.h> #include "platform.h" #include "xil_printf.h" #include "xstatus.h" #include "ps7_init.h" #include "xscugic.h" #include "xparameters.h" #include "xuartlite.h" #include "xil_printf.h" #define TEST_BUFFER_SIZE 700 u8 SendBuffer[TEST_BUFFER_SIZE]; /* Buffer for Transmitting Data */ u8 RecvBuffer[TEST_BUFFER_SIZE]; /* Buffer for Receiving Data */ XUartLite UartLite; /* Instance of the UartLite Device */ int UartLitePolledExample(u32 DeviceId) { int Status; /* * Initialize the UartLite driver so that it is ready to use. */ Status = XUartLite_Initialize(&UartLite, DeviceId); if (Status != XST_SUCCESS) { return XST_FAILURE; } /* * Perform a self-test to ensure that the hardware was built correctly. */ Status = XUartLite_SelfTest(&UartLite); if (Status != XST_SUCCESS) { return XST_FAILURE; } return XST_SUCCESS; } int main() { int ReceivedCount = 0; int i; init_platform(); //enable the pl ps7_post_config(); // xil_printf("status is %d\n\r",status1); //enable uartlite UartLitePolledExample(XPAR_UARTLITE_0_DEVICE_ID); //xil_printf("status is %d\n\r",Status2); xil_printf("Hello World, GCP!\n\r"); while(1) { ReceivedCount = XUartLite_Recv(&UartLite,RecvBuffer,TEST_BUFFER_SIZE); for(i=0; i<ReceivedCount; i++) { xil_printf("ReceivedCount[%d] = %x\n\r" ,i,RecvBuffer); } } cleanup_platform(); return 0; }
  9. gcp

    Sending AT commands

    Dear FPGA experts, Good day!!! Does anybody in this forum already tried in sending AT commands from Zedboard to the external peripheral devices? Ours, want to interface cellular module device into the pmod zedboard using the RS232(UART) connection. Hope to hear from you some enlightment. Thanks. Best regards, Glenn
  10. Hello @jon, Thanks for this. We will check the link and study the flow. Best regards, Glenn
  11. Hi all, May I humbly ask the experts in this forum if you already tried to implement AT commands into FPGA to make the cellular module works and be able to use the internet inside the FPGA. Ours, want to implement the cellular module via RS 232 interface into the pmod zedboard. Hoping for some guidance on how to go through it. Thank you in advance. Best regards, Glenn
  12. gcp

    AXI UARTLITE Data Output

    @notarobot Thanks for your immediate response, really appreciated. I will look on to it. Can I request you a guide sample application project implemented based on your above setup for us to check on ours. Thanks. Best regards, Glenn
  13. gcp

    AXI UARTLITE Data Output

    Dear FPGA experts, May I ask some valuable comments and suggestions on the experts on this forum regarding of our encoutered problem. We interface our ublox M8U gps into a xilinx zedboard using the UART-Pmod connections. Created the hardware design and routed the Ublox gps signals into the PL side using the axi-uartlite IP. Then, in SDK, we used the axi-uartlite pre built code "uartlite_polled_example.c" and take some minor changes in order to get the data directly in the ublox gps module. Running the program and printing the Received buffer was successfull.But comparing the hex data received, between the sdk and the hex data recieved using the logic analyzer are different. We pressumed that the data in the logic analyzer are correct since it was coincide with the message structuring of the ublox protocol specification manual. I also attached the code used, hardware design, logic analyzer result and the sample output data for you to validate my findings aboved. My understanding with the logic analyzer result as againts in the sdk hex data is that " header tag + class id tag + length of data bytes" should be the same. Hope to hear from you. Thanks. Best regards, Glenn
  14. Dear malexander,

    Greetings!!!

    I am a beginner of the zybo product of digilent. After following some of the tutorials online,  when we (inset Dhen) plugged it again, unfortunately, it did not power on.  May I know what are the possible problems in the setup? Is there have an impact of using high voltage power (let say 19V power input) on the board? We so much appreciate your feedback on the matter.

    Thanks and God bless you...

     

    Best regards,

    Glenn