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About wfjmueller

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  1. When I ported the w11 CPU design from Nexys4 to Nexys A7 I didn't use the SRAM to DDR component but wrote my own interface layer which queues writes and includes a 'last row buffer', see sramif_mig_nexys4d and sramif2migui_core. I had a look at the Nexys 4 DDR Xilinx MIG Project and was a bit astonished to see that the SYS_CLK was 200 MHz <TimePeriod>3333</TimePeriod> <PHYRatio>2:1</PHYRatio> <InputClkFreq>200.02</InputClkFreq> I really wonder why Digilent recommends this. It is possible to use 100 MHz, to use the board clock directly, and to avoid a PLL/MMCM to generate 200 MHz. In my design the MIG runs with 100 MHz and seems to work. So question: What was the reason use 200 MHz (and thus an additional PLL/MMCM) ?
  2. Hi, within the w11 project you'll find among many other things a very well tested UART (under rtl/vlib/serport) a set of test designs for the serial link, also for Basys3 (under rtl/sys_gen/tst_serloop) also a driver for the hex display (under rtl/bplib/bpgen, see sn_7segctl.vhd) and a set of test designs for the 'human I/O",also for Basys3 (under rtl/sys_gen/tst_snhumanio) The UART features automatic Baud rate determination (see serport_uart_autobaud.vhd) XON/XOFF handling (see serport_xonrx.vhd, serport_xontx.vhd) It supports up to 12 MBaud, and is in fact usually used with 12 MBaud. In test benches it allows even 120 MBaud, which speeds to the simulation time of full systems. It is usually used with FIFO buffering and separate system and serial clock domains (see serport_2clock2.vhd). It can of course be used in a simple single clock domain setup (see serport_1clock.vhd). Cheers, Walter
  3. Hi @JColvin, true, there might be some additional cost, e.g. in a lower impedance power net and higher rated power converters. However, the current Digilent portfolio has only quite expensive Kintex-7 boards like the Genesys 2 or the NetFPGA, both with a XC7K325T which is also beyond WebKit limits. What is imho missing is a mid-cost Kintex class board based on a XC7K70T in the $300 range, either in the Nexys4 or Arty line, or a XC7K160T in the $500 range as a follow-up of the Nexys Video as Atlys 3. Thanks, Walter
  4. Hi, First I tried with Nexys K7, here another try with Arty K7. There is now a great portfolio of Arty boards, spanning Spartan-7, Artix-7 and Zynq. The only thing missing is an Arty with a Kintex-7. And is seems imho well in reach, the XC7K70T is with ~$120 only $10 more expensive then the XC7A100T used on the Arty A7-100. So a Arty K7-70 should be possible at a reasonable price, slightly above the Arty A7-100. With that offer the Arty family would cover Arty S7 -- Spartan-7 and lowest cost Arty A7 -- Artix-7 Arty K7 -- Kintex-7 and highest speed Arty Z7 -- Zynq and embedded processor Maybe somebody from Digilent can comment on this. Or users who'd like to buy such a board  With best regards, Walter
  5. Hi, I really like the Nexys series boards, I've a Nexys2, a Nexys3 and a Nexys4 board. Artix-7 FPFAs a fine, but Kintex-7 are about a factor two faster. So I'd love to have an affordable Kintex-7 based board. There are now several Nexys variants. but why not a Nexys4 K7 with a XC7K70T or even XC7K160T. When I look at the FPGA cost a see XC7A100T-1CSG324C ~ $110 XC7K70T-1FBG484C ~ $120 XC7K160T-1FBG484C ~ $220 so a XC7K70T should be possible at a price tag still comparable to the current Nexys4 A7. Maybe somebody from Digilent can comment on this. Or users who'd like to buy such a board With best regards, Walter
  6. Is now on GitHub as part of the w11 retro-computing project. The serial port handling is under rtl/vlib/serport with UART in serport_uart_rxtx.vhd auto-bauder in serport_uart_autobaud.vhd optional XON/XOFF handling in serport_xonrx.vhd and serport_xontx.vhd There is a whole stack with elasticity FIFOs for single clock (system == serial clock) under serport_1clock.vhd for dual clock (system != serial clock) under serport_2clock2.vhd I'm using the later with 120 MHz serial clock and 12 MBaud in many designs.
  7. wfjmueller


    Hi, I just tried to generate a MIG core for Arty. Under Vivado 2015.4. Used as a starting point the prj and ucf provided by Digilent as When I imported the mig.prj the core generator complained with an ERROR about a part mismatch. A quick look into mig.prj shows <TargetFPGA>xc7a15ti-csg324/-1L</TargetFPGA> The Arty uses a 35 die size Artrix-7, not a 15 die size. Simply wrong part. If elementary things like this are wrong, how should I trust the rest ?
  8. There is no problem to use the 2nd channel of the FT2232 on Arty, Basys3 and Nexys4 boards. All you need to know is to which FPGA pins the RXD and TXD and in case of nexys4 the RTS and CTS lines of the FT2232 are connected. This is documented in the master xdc and in the reference manual. Than simply use it as USB-UART via /dev/ttyUSBx. With proper settings that works very well. I'm using this in many designs on all three boards. With baud rates of 10 and 12 MBaud and throughputs of up to 1 MByte per second. A bit of a nuisance is that only the Nexys4 has RTS/CTS connected so that hardware handshake can be used. On Basys3 and Arty I've to use XON/XOFF flow control and thus to ensure with proper escaping that these characters can be transmitted over this channel. Using flow control is a must at the speeds I use. Bottom line: the USB UART part of the FT2232 can be used a medium speed data interface. And a remark to Digillent: please connect RTS/CTS in future boards (as done on Nexys4).
  9. Hi, see solution of the issue posted on February 21st under Posting "Vivado 2015.4 MIG crashes with segmentation violation under Ubuntu 14.04 LTS" in Xilinx Forum
  10. Hello, just tried MIG for Arty with Vivado 2015.4 under Ubuntu 14.04 LTS, and also got Loading device for application Rf_Device from file '7a35t.nph' in environment /mnt/data/opt/Xilinx/Vivado/2015.4/ids_lite/ISE. child killed: segmentation violation I haven't Vivado 2015.2 installed, but tried 2014.4. This has an older MIG version (2.3 instead of 2.4) but also crashes. I've created other IP cores, e.g. microblaze, so the basic installation seems to be sound. Had somebody created the memory controller for Arty recently with an up-to-date Vivado version ? If yes, on what platform ?