tommienator

Members
  • Content Count

    6
  • Joined

  • Last visited

Everything posted by tommienator

  1. Could resolve it by splitting up the DDR memory in different regions: * 1 region for the heap/stack and all other things for core0 * 1 region for the heap/stack and all other things for core1 * 1 region that is common between both regions and can be accessed from the different CPU-cores. Using semaphores to lock certain resources so that overwriting can't occur.
  2. Hey All, So I have an application running on both ARM cores with each their specific available memory region (split in half): ARM core 0 base address: 0x100000 and size 0xFF800000 ARM core 1 base address: 0x10080000 and size 0xFF800000 Now I have a data acquisition system running on core 0 which receives data from another system and stores the received data in DDR memory and holds a pointer + length (in bytes) of the data. This pointer and length is passed to core 1 which needs to access the data in DDR for further processing and offload it to accelerators which are contro
  3. Hey @JColvin, In the end I've could fix the problem with the tutorial given by Digilent (https://zedboardupgrade.s3.us-east-2.amazonaws.com/ZedBoard+Rev+E+project+update+procedure.pdf?_ga=2.236277057.1100890869.1622904314-1810490008.1617456326). On the other hand I don't see any things considering REV E of the Zedboard on the website of Avnet (https://www.avnet.com/wps/portal/us/products/avnet-boards/avnet-board-families/zedboard/).
  4. Hey @JColvin, Thanks for the response. Considering the board file, indeed I've taken the one from Digilent (assumed this was the maintained one since Avnet didn't provide support anymore but Digilent does (read this on a certain forum post). Nevertheless, first followed your advise and installed the board file directly from Avnets Github page (bdf/zedboard/1.4 at master · Avnet/bdf · GitHub), which should, accordantly to the commit messages, support Vivado 2020.2. But this is for revision D I've noticed. Nevertheless, this didn't resolve the problem. Just double checked the revision,
  5. Hey all, I've got a small and probably stupid problem. Upgraded my Vivado to version 2020.2 and setup the basic Zynq hello world tutorial but it seems nothing comes out of the UART side. Little summary with print screens to make it as clear as possible... So first of all, I've downloaded the latest board files from Digilent (Github) and installed them accordantly. Next created a rudimentary board design with the Zynq processing system instantiated and UART 1 strapped to MIO 48 - 49 as is required (see print screen below). Board design check completes without any problem.
  6. tommienator

    Pmod DA3

    Hey everybody, A small question. I need to generate a signal of 28.8MHz (sine wave), so in FPGA I've build a DDS and it's generating a nice sine wave @ 27.799MHz (close enough :p). For connecting this to a certain target board I've bought the PMOD DA3 (https://store.digilentinc.com/pmod-da3-one-16-bit-d-a-output/). There is only one small problem that I can't figure out... I know when you're sampling you have to comply to Shannon's theory, but how is it with DACs when you are reconstructing a signal, do they also have to comply to this? I've dived into the schematic of the PMOD DA3