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  1. Thanks for the fast answer and your help, now everything is working correctly. The FDwfDigitalOutEnableSet has to be called at least in cofiguration of eack channel, otherwise a peak will generated and the external scope will trigger on its edge. The FDwfDigitalOutWaitSet has to be called before FDwfDigitalOutEnableSet. Another issue after generating VIs from dwf.dll is that the parameter "rgBits" in FDwfDigitalOutDataSet has to be modified to a pointer, otherwise its not possible to use a custom data number as a bit mask. Best regards Evgeni
  2. Hi attila, thank you very much for the fast answering! I have installed all possible LabVIEW drivers and projects from the links you send me and I have also imported the dwf.dll manually already. Then I have modified the "Digilent_WaveForms_Stimulus Response (MSO and FGEN)" to a Logic Analyzer and it works verry well. I have also tried to implement in LabVIEW a pattern generator with your python code above, but any of the signal lines does not work yet. Firstly I tried to generate a digital clock signal with 1MHz and display it on a external scope (Agilent DSO-X-3024A), but nothing happens. I have attached the VI and some screens of the VI's block diagram and hope you or anyone else can help me. The VI consists of a mix of LabVIEW generated VIs from dwf.dll and VIs from NI's Edition drivers (https://decibel.ni.com/content/docs/DOC-44838). My final destination in pattern generation is shown in the Image below "What_I_want_to_generate" via LabVIEW: (Note: The frequency is 2 MHz, but in the VI is 1 MHz). Thanks in advance for your help. Evgeni Digilent_WaveForms_Pattern_Generator.vi
  3. Hi there, isn't there any finished VI solution in LabVIEW, how to use the Pattern Generator and the Logic Analyzer. I have to simulate a SPI interface (3 lines with Pattern and 4 line Logic Analyzer). I tried the static DIO from NI Community, https://decibel.ni.com/content/docs/DOC-44838 but I need a continously mode with 2MHz frequency like Chris in the post above, not the static one... Would be verry happy to get some VI for continously generating pattern and logic analizing. Thanks for helping in advance. Evgeni