TJ

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  1. Hello Arthur, Thanks much. How would you recommend that I implement the counter and make it 1 second in the vhdl code? I am not understanding. Thanks, TJ
  2. How do add a 1 second delay when verifying each RAM data/address one at a time last process of code? Sparten -3E using xc3s100 device. Xilinx P.20131013 version ISE Project Navigator. Regarding the following process if I comment out two of the three then the one not commented out reads the correct LCD values based on the RAM reading of dataout and address. Any idea how to put in about a 1 second delay between each of the below so that I can see the LCD values change everytime I confirm each correct reading from RAM: process -- Which LCDs to turn on based on reading data from RAM process begin -- How to add a one second delay between each time I read specific data from RAM if DataOut1 = x"AA" and Address1 = x"04" then an<="0000"; ssg<="11111001"; end if; --confirmed "1" if DataOut2 = x"55" and Address2 = x"06" then an<="0000"; ssg<="10100100"; end if; --confirmed "2" if DataOut3 = x"78" and Address3 = x"08" then an<="0000"; ssg<="10110000"; end if; --confirmed "3" end process; ---------------------------------------- The below is my VHDL code: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; entity RAM is Port ( mclk, Reset, WriteEn, Enable : in STD_LOGIC; an : inout STD_LOGIC_VECTOR (3 downto 0); --LCDs ssg : out STD_LOGIC_VECTOR (7 downto 0) -- 7 Segment Display ); end RAM; architecture Behavioral of RAM is type Memory_Array is array (0 to (2 ** 8) - 1) of STD_LOGIC_VECTOR (7 downto 0); signal Memory : Memory_Array; signal DataIn, Address, DataOut : STD_LOGIC_VECTOR (7 downto 0); signal DataOut1, DataOut2, DataOut3 : STD_LOGIC_VECTOR (7 downto 0); signal Address1, Address2, Address3 : STD_LOGIC_VECTOR (7 downto 0); begin process (mclk) -- Write process begin if rising_edge(mclk) then if Reset = '1' then -- Clear Memory on Reset Memory <= (others => (others => '0')); elsif Enable = '1' then if WriteEn = '1' then -- Store DataIn to Current Memory Address Address<=x"04"; DataIn<=x"AA"; Memory(to_integer(unsigned(Address))) <= DataIn; Address<=x"06"; DataIn<=x"55"; Memory(to_integer(unsigned(Address))) <= DataIn; Address<=x"08"; DataIn<=x"78"; Memory(to_integer(unsigned(Address))) <= DataIn; end if; end if; end if; end process; process (mclk) -- Read process begin if rising_edge(mclk) then if Enable = '1' then if WriteEn = '0' then -- Read Memory Address1 <= x"04"; DataOut1 <= Memory(to_integer(unsigned(Address))); Address2 <= x"06"; DataOut2 <= Memory(to_integer(unsigned(Address))); Address3 <= x"08"; DataOut3 <= Memory(to_integer(unsigned(Address))); end if; end if; end if; end process; process -- Which LCDs to turn on based on reading data from RAM process begin if DataOut1 = x"AA" and Address1 = x"04" then an<="0000"; ssg<="11111001"; end if; --confirmed "1" if DataOut2 = x"55" and Address2 = x"06" then an<="0000"; ssg<="10100100"; end if; --confirmed "2" if DataOut3 = x"78" and Address3 = x"08" then an<="0000"; ssg<="10110000"; end if; --confirmed "3" end process; end Behavioral; Thanks much.
  3. hamster, I am now reading ram correctly! Bless you heart! Thank you so much for everything! TJ
  4. hamster, Thank you so much! I really appreciate all of your inputs. I was up until 230 am last night/this morning. I will start coffee pot again this evening and try your recommendations. Thanks again, TJ
  5. Hello Davep238, hamster, or anyone else, I am really under a huge amount of stress right now trying to get my RAM to function properly. It is not reading correct. Please see my below VHDL code and test bench. Any ideas why I am not able to successfully read from my ram? For your convenience I attached my vhdl code so you can try it using my test bench. Thanks much. LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; entity RAM is Generic ( DATA_WIDTH : integer := 8; ADDRESS_WIDTH : integer := 8 ); Port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; DataIn : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0); Address : in STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0); WriteEn : in STD_LOGIC; Enable : in STD_LOGIC; DataOut : out STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0) ); end RAM; architecture Behavioral of RAM is type Memory_Array is array ((2 ** ADDRESS_WIDTH) - 1 downto 0) of STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0); signal Memory : Memory_Array; begin -- Read process process (Clock) begin if rising_edge(Clock) then if Reset = '1' then -- Clear Memory on Reset for i in Memory'Range loop Memory(i) <= (others => '0'); end loop; elsif Enable = '1' then if WriteEn = '0' then -- Read Memory DataOut <= Memory(to_integer(unsigned(Address))); end if; end if; end if; end process; -- Write process process (Clock) begin if rising_edge(Clock) then if Reset = '1' then -- Clear Memory on Reset for i in Memory'Range loop Memory(i) <= (others => '0'); end loop; elsif Enable = '1' then if WriteEn = '1' then -- Store DataIn to Current Memory Address Memory(to_integer(unsigned(Address))) <= DataIn; end if; end if; end if; end process; end Behavioral; -- beginning of test bench LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.NUMERIC_STD.ALL; ENTITY TB_RAM IS END TB_RAM; ARCHITECTURE behavior OF TB_RAM IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT RAM PORT( Clock : IN std_logic; Reset : IN std_logic; DataIn : IN std_logic_vector(7 downto 0); Address : IN std_logic_vector(4 downto 0); WriteEn : IN std_logic; Enable : IN std_logic; DOut : OUT std_logic_vector(7 downto 0) ); END COMPONENT; --Inputs signal Clock : std_logic := '0'; signal Reset : std_logic := '1'; signal DataIn : std_logic_vector(7 downto 0) := (others => '0'); signal Address : std_logic_vector(4 downto 0) := (others => '0'); signal WriteEn : std_logic := '0'; signal Enable : std_logic := '0'; --Outputs signal DOut : std_logic_vector(7 downto 0); -- Clock period definitions constant CLK_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut : RAM PORT MAP ( Clock => Clock, Reset => Reset, DataIn => DataIn, Address => Address, WriteEn => WriteEn, Enable => Enable, DOut => DOut ); -- Clock process definitions CLK_process : process begin Clock <= '0'; wait for CLK_period/2; Clock <= '1'; wait for CLK_period/2; end process; -- Stimulate Control process stim_main : process begin wait for CLK_period * 1; Reset <= '0'; WriteEn <= '1'; wait for CLK_period * 1; end process; -- Stimulate Write process stim_write_read : process begin -- write wait for CLK_period * 1; Address <= "00000"; for i in 0 to 2 loop WriteEn <= '1'; Enable <= '1'; Address <= Address + 4; DataIn <= DataIn + 3; wait for CLK_period * 1; end loop; -- read Address <= "00000"; for k in 0 to 2 loop WriteEn <= '0'; Enable <= '1'; Address <= Address + 4; wait for CLK_period * 1; end loop; wait; end process; end; RAM_3_18_2016R1.vhd
  6. Davep238, Thank you so much and great catches! You are correct I only read when write enable is 0. I need to make proper connections in test bench. I agree. I need to initialize addresses to zerp before looping. I need to remove my infinite loop. Thanks again, TJ
  7. Hello, Please see my RAM VHDL code and RAM test bench. Does anyone have any idea why I can only write but not read from RAM? Please see below: LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.NUMERIC_STD.ALL; entity RAM is Generic ( DATA_WIDTH : integer := 8; ADDRESS_WIDTH : integer := 8 ); Port ( Clock : in STD_LOGIC; Reset : in STD_LOGIC; DataIn : in STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0); Address : in STD_LOGIC_VECTOR (ADDRESS_WIDTH - 1 downto 0); WriteEn : in STD_LOGIC; Enable : in STD_LOGIC; DataOut : out STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0) ); end RAM; architecture Behavioral of RAM is type Memory_Array is array ((2 ** ADDRESS_WIDTH) - 1 downto 0) of STD_LOGIC_VECTOR (DATA_WIDTH - 1 downto 0); signal Memory : Memory_Array; begin -- Read process process (Clock) begin if rising_edge(Clock) then if Reset = '1' then -- Clear DataOut on Reset DataOut <= (others => '0'); elsif Enable = '1' then if WriteEn = '1' then -- If WriteEn then pass through DIn DataOut <= DataIn; else -- Otherwise Read Memory DataOut <= Memory(to_integer(unsigned(Address))); end if; end if; end if; end process; -- Write process process (Clock) begin if rising_edge(Clock) then if Reset = '1' then -- Clear Memory on Reset for i in Memory'Range loop Memory(i) <= (others => '0'); end loop; elsif Enable = '1' then if WriteEn = '1' then -- Store DataIn to Current Memory Address Memory(to_integer(unsigned(Address))) <= DataIn; end if; end if; end if; end process; end Behavioral; -- beginning of test bench LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.NUMERIC_STD.ALL; ENTITY TB_RAM IS END TB_RAM; ARCHITECTURE behavior OF TB_RAM IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT RAM GENERIC ( DIN_WIDTH : integer := 8; ADDR_WIDTH : integer := 5; ADDR_COUNT : integer := 32 ); PORT( CLK : IN std_logic; RST : IN std_logic; Din : IN std_logic_vector(7 downto 0); Addr : IN std_logic_vector(4 downto 0); Wr_En : IN std_logic; En : IN std_logic; DOut : OUT std_logic_vector(7 downto 0) ); END COMPONENT; --Inputs signal CLK : std_logic := '0'; signal RST : std_logic := '1'; signal Din : std_logic_vector(7 downto 0) := (others => '0'); signal Addr : std_logic_vector(4 downto 0) := (others => '0'); signal Wr_En : std_logic := '0'; signal En : std_logic := '0'; --Outputs signal DOut : std_logic_vector(7 downto 0); -- Clock period definitions constant CLK_period : time := 10 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut : RAM PORT MAP ( CLK => CLK, RST => RST, Din => Din, Addr => Addr, Wr_En => Wr_En, En => En, DOut => DOut ); -- Clock process definitions CLK_process : process begin CLK <= '0'; wait for CLK_period/2; CLK <= '1'; wait for CLK_period/2; end process; -- Stimulate Control process stim_main : process begin wait for CLK_period * 10; RST <= '0'; wait for CLK_period * 10; En <= '1'; wait for CLK_period * 112; En <= '0'; wait for CLK_period * 16; RST <= '1'; wait for CLK_period * 16; RST <= '0'; En <= '1'; wait; end process; -- Stimulate Write process stim_write : process begin wait for CLK_period * 20; for i in 0 to 31 loop Wr_En <= '1'; Din <= Din + 3; wait for CLK_period * 1; Wr_En <= '0'; wait for clk_period * 2; end loop; wait; end process; -- Stimulate Read process stim_read : process begin --wait for CLK_period * 1000; wait for CLK_period * 20; --Wr_En <= '0'; loop Addr <= Addr + 7; wait for clk_period * 1; end loop; wait; end process; end;
  8. Hello hamster, No test plan yet but when I do I will let you know if I have questions. Thanks again. I do have test bench set up reading and writing data using variables but not yet RAM. Thanks again .
  9. Hello Hamster, Thank you very much. I agree the "re" and "we" does not need to be in sensitivity list. I agree the read and write should be in same process. Do you know of a test bench recommendations for this? Thanks, TJ
  10. Hello, Does anyone know of a good VHDL test bench reference for the following VHDL code? Also, does my below RAM VHDL code make sense? Thanks, TJ Pseudo Dual Port VHDL Example library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_arith.all; use IEEE.std_logic_unsigned.all; entity daul_port_ram is generic (data_width : natural := 8; addr_width : natural := 16); port ( clk_in : in std_logic; clk_out : in std_logic; we, re : in std_logic; addr_in : in std_logic_vector( addr_width - 1 downto 0); addr_out : in std_logic_vector( addr_width - 1 downto 0); data_in : in std_logic_vector( data_width - 1 downto 0); data_out : out std_logic_vector( data_width - 1 downto 0) ); end daul_port_ram; architecture daul_port_ram_arch of daul_port_ram is type mem_type is array (2** addr_width downto 0) of std_logic_vector( data_width - 1 downto 0) ; signal mem : mem_type ; begin mem_write : process (clk_in, we) begin if clk_in'event and clk_in = '1' and we = '1' then mem( conv_integer( addr_in)) <= data_in ; end if ; end if ; end process write ; mem_read : process (clk_out, re) begin if clk_out'event and clk_out = '1' and re = '1' then data_out <= mem( conv_integer( addr_out)) ; end if ; end process read; end daul_port_ram_arch;
  11. Yes that does makes sense. Thanks much, TJ
  12. Hello thank you very much. I will try it.
  13. TJ

    8 bit even parity check

    Thank you very much. Yes I did mean parity. Spelling error. The 3 use statements is old habits. Good point about temp2 variable. Thanks, TJ
  14. Hello, In vhdl, does anyone know how to handle underflows or any reference material available? I am working on underflow for decrementing bit vectors. I am confused about underflow. Thanks, TJ
  15. Hello, Does anyone have any recommendations for a vhdl function that converts Integer to std_logic_vector function? Thanks, TJ