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davec last won the day on February 9 2016

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  1. Problems with MIG_7

    Actually, New\arty-a7-35\E.0\part0_pins.xml has the wrong io location for my board also: <pin index="64" name ="shield_dp0_dp19_tri_i_10" iostandard="LVCMOS33" loc="C1"/> The file "old\board_parts\artix7\arty\C.0\board_part.xml" has the correct pin: <pin index="10" iostandard="LVCMOS33" loc="V17"/> Perhaps I originally compiled with Vivado 2014.4, and now I have been using 2015.3? Is this why the format of the board files are different? I don't understand the V17 <-> C1 pin swap though.
  2. Problems with MIG_7

    My Arty board has the XC7A35T, running Vivado 15.3 This may be part of my problem. I figured the mig file was corrupted so I re-copied the board files into the Vivado board files directory, and I used the ARTY folder from the vivado-boards-master.zip file called "New\Arty\C.0". This got me out of that vivado hang (but only when I manually go through each step of implementation). I think I should have used the ones from the arty-a7-35 folder, because now my gpio signal for shield_dp0_dp19_tri_io[10} disappeared from pin V17 (as the arty schematic shows also) and is now on pin C1 of the FPGA. Should I be using "New\arty-a7-35\E.0" ? thanks
  3. Problems with MIG_7

    Sorry for such a vague question. I am using the Arty board. It's probably a file corruption problem and more related to Vivado, but for some reason all of a sudden (it used to work fine) when I bring up my block diagram and click on the mig_7series block it hangs forever while trying to open the block to re-customize. I have even deleted the block, and when I try to bring it back in from the list of IP, the same thing happens- it hangs trying to load the block onto the diagram. i have even brought my design into 2017.4 and same problem- it hangs trying to load that one module. I can re-customize any other block in my design with no problems. I think if I can just find where all the files for that IP are located I can replace them without having to re-install all of vivado. Another hint is that I can't bring that mig_7series block into other designs either, without vivado hanging. I can't seem to find any log file with a related error either. thanks, dave
  4. Problems with MIG_7

    Has anyone had problems trying to use MIG_7 in their block diagrams in Vivado? I had a design that was working under version 2015.3, then something went wrong. Whenever I try to select that IP block in my diagram, vivado hangs trying to open it. I tried deleting it from my design and bring in a new mig_7series block from my list of board components and it hangs as well. I brought my design over onto a different Win7 computer and did a fresh install of a newer vivado 2017.3 with the latest board files with the exact same result- when I try to bring in the mig block, vivado hangs forever. Anyone know which files in my design I can remove to eliminate the bad references to the mig_7? tnx
  5. How to program Arty flash

    At first I was thinking maybe the FPGA didn't finish loading or the power up reset isn't coming up clean, but you said the done light comes on. If it is an intermittent problem, Is it possible that your SPI CLK is too fast for the flash part that you are using? You can set that in the HDL code. Maybe your application reset vector is not at the correct location or not getting loaded from cold reboot? Does the PROG button work every time, or only after you flashed the part? In my design, the FPGA bit file loads, along with bootloader into FPGA RAM. The bootloader then runs and copies my application into DRAM and then jumps to my start of application in DRAM. With a scope, you can see if there is any activity between the flash and DRAM after DONE comes up.
  6. Board Geometry for ARTY

    The dimensions you have in question are on the same 0.100" grid as the connectors above (0.291" from the edge of the board. The next header to the left just skips a pin. If I remember correctly, the two outside rows are spaced to line up with an Arduino shield.
  7. How to program Arty flash

    Thanks Tom and J- It's all running now.I am using the srec_bootloader from SDK. I looked everywhere and did not see a reference to C_USE_STARTUP. I guess it was a carry over from a previous design. How (and where) would I set a PARAM_VALUE if I wanted to?
  8. How to program Arty flash

    I figured out why the sck signal is not getting implemented- For some reason, "PARAM_VALUE.C_USE_STARTUP" is not set to zero, so when the file "board.xit" does not see this variable =0, it does not implement the sck pin (L16). I cheated and took out this test in "board.xit" (because I don't know where that PARAM_VALUE gets set). I added constraints for the pin: set_property PACKAGE_PIN L16 [get_ports qspi_flash_0_sck_io] set_property IOSTANDARD LVCMOS33 [get_ports qspi_flash_0_sck_io] and I now get a clock to the QSPI flash when the bootloader runs. One last step to solve- where to put my user program in flash that the bootloader will copy into DDR. The tools don't tell me how large the FPGA config file is (with compression on). I looked at the file size of the .bin file and rounded up to the next 1K, but I wish there was a programmatic way to do this from Vivado. Hurray- On power-up I can now config the FPGA, run the bootloader in block ram, which then copies my large user program from flash to DDR and executes.
  9. How to program Arty flash

    Thanks, mskreen. I managed to load the FPGA along with a bootloader program (srec_bootloader) from flash! The user code that I ultimately want to run does not fit into block ram, hence it must be moved from flash to DDRAM by the bootloader that is running in blockram. Now my problem is that as I mentioned above, I am not seeing the SCK run once the bootloader executes. My block design has an axi_quad_spi, but the sck_o and sck_t signals don't come out to the outside world, only io[3:0] and ss signals. I tried adding the signals in the hdl wrapper, but they get blown away when I resynthesize because they don't appear on my block design. Any ideas- from anyone who has implemented flash on the Arty? TNX
  10. How to program Arty flash

    Thank you J, Part of the question may be when the bootloader runs and it loads my .mcs into the Quad SPI Flash should it be clocking the flash via FPGA pin L16? I don't see that this pin is configured. I understand that normally when the FPGA loads, it uses CCLK, etc, but I am talking about when I am programming the bootloader and my code into the flash. When I run the bootloader code, I get the opening prompt "SREC SPI Bootloader", but when tracing the code, it fails when initializing and/or accessing the SPI flash. Also, I am confused as to what to use for FLASH_IMAGE_BASE_ADDR. Is that the offset into flash where my user code starts (after the FPGA bits and bootloader code) or where the bootloader sits? Surely someone has been successful in booting an FPGA design with bootloader and user code from flash on the Arty? TNX
  11. How to program Arty flash

    I'm still spinning my wheels on this one. I need to put the bootloader program, my FPGA design, and my application program into the flash on Arty so that the bootloader will load my code on power up. I am trying to do this from the SDK but haven't got it to work yet. Any ideas?
  12. How to program Arty flash

    Thanks mskreen, but it looks like that only puts the FPGA bit file from Vivado into the flash. I also need my code from SDK to load on bootup. I have been reading xilinx AR #63605 and AR#64238, but still don't have it right.
  13. How to program Arty flash

    So I created a microblaze design on Arty in Vivado 2015.3 with lwIP axiether and some GPIO to control my external hardware. I wrote my C code in SDK. From SDK, I can download the FPGA config and then run my C code on Arty by doing Run -> Run As -> 1. Launch On Hardware. Everything works great! Now I want to put this all in flash so it will come up on power-up reset. I read Xilinx #63605, how to create an MCS boot image, but I am confused. Do I need to include an axi_quad_spi in my block design, or does the SDK flash programmer take care of this? (I don't need SPI in my design otherwise). I'm not sure what files to combine into the mcs. Is there a tutorial on this subject? Thanks- Arty is a great product!
  14. Board Geometry for ARTY

    Are there dimensions available somewhere for the Arty board? I want to design a shield for Arty and need to know the exact locations of the headers. I see that it looks similar to Arduino headers, but a drawing or even Altium PCB file would really help! Thanks.