SteveD

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  1. Hey Tom. I tried this project and I have had some issues. To be honest, its more likely SW "newbie" issues from me than anything else. I'm a HW guy a heart, not really an embedded SW guy. The Xilinx SDK kind of scares me alot. I was hoping I could step through a similar previous example (the OOTB GPIO demo) to see if I could figure out how to get the SDK to work. I managed this with the OOTB demo, but I think I'm lost with this one. I did the Vivado build and got a bit stream, and exported it for the SDK. That was OK, kind of. Co-incidently I always get timing violations (4 of them) with the uBlaze, but this is not the issue. Like I said I can generate the bit-file. My biggest issue is within the SDK, I could never seem to get it to successfully program the FPGA, using the system_wrapper BIT/MMI files, together with the ELF that I believe comes with the project (using this instead of bootloop). It "runs" but nothing on the display. And I'm not sure how I suck in the newly created bitfile, the C-code, etc. Its all a bit black magic to me. Setting up the right repositories maybe. BTW as an aside, I did go and right up a simple state machine in Verilog to try and send the SPI commands to the display. No MCU, just a few state machines. I must have some sequencing issue, as the display flashes briefly, but no red line appears as planned. Oh well. Are you planning on adding some step by step instructions for the SDK? Just wondering. Thanks Steve
  2. Hey Tom, Excellent. Thanks for all this work. I'll see if I can get something going. I have the design read into Vivado, and just trying to understand what you did. Last night I also coded up a simple SPI statemachine to just try to get something (anything) written into the PMOD. I mean pure Verilog with no uBlaze. If I could initialize the board and then draw a red box and a green line I would have been happy. Was just about to try all that before you sent this better way forward:-) I see some big clocks in there: 200MHz and other odd ratios.... Thanks Steve
  3. Which MicroBlaze project are you referring to? For the OOTB GPIO/LED project, I did the changes that Tom suggested above, and that worked. Seems strange that the original Avnet design had an error that means the design won't go through synth. I did use the "new" board files too. As for the topic of this thread, the OLEDrgb PMOD.... No nothing new here. I have precisely zero information on the chip that drives the RGB panel, so hard to know what to do. They give a power up and power down sequence, but nothing in terms of how/what to drive the SPI with. No registers, no nothing. So the module I purchased from Digilient is pretty much useless right now. Wasted $29.99. Which came to almost $45 Canadian with shipping/tax/fx/etc. That kind of money would have bought me a beer at a Canucks game! Eagerly awaiting something from Tom that he mentioned above. Some example project with driver code for that display. It does seem a bit strange that Diligent would sell something that no-one can actually use. I even tried to get a data sheet directly from the chip manufacturers in HongKong (Solomon Systech SSD1331) but no response.
  4. Hey Tom, thanks for the response. Looking forward to your uBlaze project. I will also check out the Pmod OLED as you suggest. Not sure if you were involved in the other uBlaze project for Arty (i.e. the OOB GPIO/LED example) but I had an issue with that one. Basically I can't get it to synthesize to due issues with L16 pin. No idea what the issue is. I entered another thread on this. I did however manage to just use the bit file for the design and make various changes with the SDK to generate the ELF, and then do the merge with the SDK, both directly to FPGA and also by overwriting the Flash image. However, after trying various changes, I still can't get the design (from the project files with no change) to get through synth. Thanks Steve
  5. Hi, I am running through the ARTY OOB GPIO demo, and have had no end of issues (Had to install older 2015.2 to even get the tcl to load, file locations, etc). I did get the batch file to run the FPGA load, and can see the terminal responses. Looks same as the built-in demo, except loaded from the USB. So that's all good. Want to play with SW changes, so went on to getting the design loaded.... Eventually got the demo to page 21 of the manual.... - Design is read in now OK - have block diagram, XDC, etc However, when I attempt to generate a bitstream, it complains at the synth stage: [Vivado 12-1411] Cannot set LOC property of ports, Terminal qspi_flash_sck cannot be placed on L16 (IOB_X0Y43) because the pad is already occupied by terminal qspi_flash_sck_t possibly due to user constraint ["c:/users/steve/desktop/Arty_stuff/7A35T_Arty_OOB_GPIO_demo_VIV2015_2/ipi/project_1/project_1.srcs/constrs_1/imports/xdc/design_1.xdc":9] To be clear, I haven't changed anything. This is just straight out of the demo. I did try to comment out the pin L16 constraint to see what happens. It got further.... synth and implementation completes, but it then falls over at the bitstream stage. Do I have the wrong board definition file (or version) or something? Thanks Steve
  6. Kind of new to the world of FPGA tinkering. Just bought an ARTY board and the OLEDrgb pmod. Struggling to find some verilog code for the SPI driver, together with some simple demo that I could use with Vivado, perhaps a simple MicroBlaze code snipet that drives the display. I could then use this a base going forward. Does anyone recommend anything here? Thanks Steve