ASICs

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  1. Hi, Generally if I don't have the outputs consumed by another device I don't worry about the warnings, however, Xilinx recommends that ALL I/O be constrained to make sure that the tool doesn't work too hard in the wrong area when implementing the timing closure. That said, you might want to take a look at this Xilinx quick take video : https://www.youtube.com/watch?v=hX7LpZlSmyo if you do not know how to constrain outputs in an XDC file (<top_level>.xdc). I hope this helps, Paul
  2. Hi everyone, I'm sure that someone has used a PLL in an Arty design....I have tried and keep getting an implementation error as follows: [DRC 23-20] Rule violation (REQP-1712) Input clock driver - Unsupported PLLE2_ADV connectivity. The signal xilinx_ip_pll/inst/clk_in1 on the xilinx_ip_pll/inst/plle2_adv_inst/CLKIN1 pin of xilinx_ip_pll/inst/plle2_adv_inst with COMPENSATION mode ZHOLD must be driven by a clock capable IO. The Arty Clock100 comes in on Pin E3, so I'm assuming that this is a clock capable input..? (can't be moved...) I even tried instantiating a BUFH in the top level before the
  3. Thank you for your input....It was in fact just a warning due to "no debug logic", I found that the "reset" to the PLL was not connected properly so the rest of the logic had no clock from the PLL.... I'm new to Vivado so I assumed I was doing something really bad (other than a wiring cockpit error!).... Thanks Again!
  4. Hello All, Just joined the forum, I just received my Arty board, and ported a very simple 32 bit counter design that drives LEDs (slower bits). I can synthesize and implement the design (no warnings), I can view the schematic and it looks exactly like the RTL, however, when I try to load it onto the target I get the following warning: WARNING: [Labtools 27-3123] The debug hub core was not detected at User Scan Chain 1 or 3. Resolution: 1. Make sure the clock connected to the debug hub (dbg_hub) core is a free running clock and is active OR 2. Manually launch hw_server with -e "set xsdb-user-