Hi This might be a bug from Xilinx, but I'm getting the following error when upgrading the IP on the Arty Base System Design : [IP_Flow 19-3475] Tcl error in ::ipgui_system_mig_7series_0_0::updateAllModelParams procedure for BD Cell '/mig_7series_0'. Loading device for application Rf_Device from file '7a35t.nph' in environment C:/Xilinx/Vivado/2015.4/ids_lite/ISE. child killed: segmentation violation I'm running this on a Win 7 x64 machine, The strange thing is I successfully generated a Mig project last week, but when I went to modify it today I ran into a similar problem. I tried reinstalling Vivado to make sure the MIG executable didn't get corrupted, but I'm still having the same problem. If the board support files are being fixed please let me know. If not if you could forward this to Xilinx I would really appreciate it.