qasddd

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  1. I'm just...so lost (shift register)

    Currently I'm trying to implement a shift register with a clock divider (to blink leds one by one in a row). To begin, I'm sorry. I know this code is not super hot. I'm very new to pretty much everything related to fpgas (embedded systems, verilog, coding in general) So, I am...very lost. This is what I've been able to put together so far. I'm pretty ok with the D flip-flop and clock divider (these work in simulation), but the shift register? I'm not even sure if I'm going about it right. Simulation runs but the led output is all the same, and thats no good. So, what am I doing wrong? D flip-flop: module d_ff( input D, input clk, input rst, output reg Q ); always @ (posedge (clk),posedge (rst)) begin if (rst == 1) Q = 8'd1; else Q = D; end endmoduleClock divider: module clk_divider( input rst, input clk, output Q ); wire [26:0] din; wire [26:0] clkdiv; d_ff d_ff0 ( .clk(clk), .rst(rst), .D(din[0]), .Q(clkdiv[0]) ); genvar i; generate for(i = 1; i<27; i=i+1) begin : d_ff_gen_label d_ff d_ff_inst ( .clk(clkdiv[i-1]), .rst(rst), .D(din[i]), .Q(clkdiv[i]) ); end endgenerate; assign din = ~clkdiv; assign Q = clkdiv[26]; endmodule Shifter: module shift_reg( input En, input rst, output [7:0] led ); //connector wire between flipflops wire [7:0] bitshift; // creating the shifter out of d flipflops //1st one d_ff d_ff0( .D(bitshift[0]), .clk(En), .rst(rst), .Q(bitshift[1]) ); //middle ones genvar i; generate for (i=1; i<7; i=i+1) begin : d_ff_gen_label0 d_ff d_ff_inst1( .clk(En), .rst(rst), .D(bitshift[i]), .Q(bitshift[i+1]) ); end endgenerate; //last one d_ff d_ff1( .clk(En), .rst(rst), .D(bitshift[7]), .Q(bitshift[0]) ); assign led = bitshift; endmodulewrapper code: module wrapper( input rst, input clk, output [7:0]led ); wire clk_connector; clk_divider clk_div1( .rst(rst), .clk(clk), .Q(clk_connector) ); shift_reg shiftreg1( .En(clk_connector), .rst(rst), .Q(led) ); endmodule
  2. Hello! I'm self-teaching myself how to program and use FPGA's, and I'm using the learn digilent digital projects as part of this endeavor. I've made it past digital project 5 (multiplexer, decoder, encoder, and shifter) just fine. BUT in project 6 (hierarchical design in verilog) I'm having some issues. The thing is, project 5 had us code these different circuits using arrays, which are NOT used in project 6. The input/output organization is different, and its just very confusing for a beginner, which these tutorials are aimed for. If someone has any example code for project 6, I would love to have a look at it. I know once I see how its done it'll be easy, but for now I'm struggling a fair amount. Also, as an extra bonus point question, is there any way to assign multiple parts of an array to different constants in a case statement? Like: case (I) 2'b0: Y[0] = 4'b0; Y[1] = 4'b1;but that won't give me an error message? or is this just not possible?