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  1. FR

    Large Spectrum Generation

    Dear All I want to generate a Spectrum having bandwidth as large as 20Mhz . the hardware I am using has realtime 56MHz Bandwidth . I am generaing a single tone (1Mhz) from DDS and then feed the signal to DAC and transmit the signal . Sweep is one of the option but because of time constraint , I want to explore other options .is it possible to use Frequency modulation or some other technique . yours suggestion will be highly appreciated . BR
  2. Dear All I want to generate an arbitrary waveform or tone having bandwith as large as 20 MHz . I am using ADRV9361-z7035 hardware from analog devices . I gone through online material , but I found material related to LTE waveform , DSSS etc .So I dont want to generate a tone or spectrum of particular standard . I am very curios that how this be done ? as the SDR I am using has 56 MHz (real time instantaneous BW ). Best Regards
  3. FR

    Passing FFT result to DDS

    Thanks for your reply. let me again elaborate my problem. I interfaced real ADC hardware with FPGA . I am injecting analog RF signal through ADC for further processing , I am using Xilinx FFT core . as i mentioned in previous post , I successfully got the peak on the correct index after performing FFT of the incoming signal . I also interfaced DAC with FPGA . So i want to regenerate RF signal through DAC on the detected bin ( the bin that came after performing FFT ). and test it on spectrum analyzer. so my understanding is that i can regenerated the signal through DDS using the inde
  4. FR

    Passing FFT result to DDS

    Dear All - I successfully implemented FFT after help and guidance ( ) .Now i want to pass the detected frequency to DDS ( My goal is to re-generate the detected frequency (FFT bin ) using DDS ) . So i need your guidance. CORDIC IP core can be use ? or some thing else you suggested. BR FRK
  5. Dear Sir Thanks again for your suggestions. I tried to answer your questions first. Then I tried to put my data and assumptions regarding this design. You mentioned that your FFT and FIFO are both running at 100MHz. May I assume that this is your system clock rate? I have used the this FIFO for clock domain crossing. FIFO's input clock is running at 61Mhz and output clock is running at 100Mhz. I'm passing the data from FIFO output to FFT core input. My FFT core is running at 100Mhz. Looking at your image above, it appears as though you have a much lower data rate th
  6. Thanks for your answer .I will update this thread with all the required details by tomorrow
  7. I had inserted FFT core in a design after FIFO .at the output i am expecting a frequency bin on certain index but i am not getting the result.FFT core is working on 100mhz clock . Following steps i had implemented . - For FIFO to be work on 100 MHz, I verified this by sending the captured data to MATLAB and analyze DATA over there. So I received data correctly. - I inserted FFT core after ADC_FIFO in the reference design. That FIFO working correctly on 100MHz clock. But I didn’t get the correct DATA from the core. For verifying FFT core settings,
  8. Dear All I have bought NEXYS 4 recently . I have basic knowledge of VHDL . Now I want to go further in digital design system.Please suggest me some good books or video or guide me. I will be very thankful I have NEXYS 4 board and Xilinx 14.2 software installed on my PC.