FR

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  1. FR

    Passing FFT result to DDS

    Thanks for your reply. let me again elaborate my problem. I interfaced real ADC hardware with FPGA . I am injecting analog RF signal through ADC for further processing , I am using Xilinx FFT core . as i mentioned in previous post , I successfully got the peak on the correct index after performing FFT of the incoming signal . I also interfaced DAC with FPGA . So i want to regenerate RF signal through DAC on the detected bin ( the bin that came after performing FFT ). and test it on spectrum analyzer. so my understanding is that i can regenerated the signal through DDS using the index number (bin number) ???? As at this time i am not worried about the phase of the incoming signal. Best Regards FRK
  2. FR

    Passing FFT result to DDS

    Dear All - I successfully implemented FFT after help and guidance ( ) .Now i want to pass the detected frequency to DDS ( My goal is to re-generate the detected frequency (FFT bin ) using DDS ) . So i need your guidance. CORDIC IP core can be use ? or some thing else you suggested. BR FRK
  3. Thank you very much. This solved my problem.
  4. Dear Sir Thanks again for your suggestions. I tried to answer your questions first. Then I tried to put my data and assumptions regarding this design. You mentioned that your FFT and FIFO are both running at 100MHz. May I assume that this is your system clock rate? I have used the this FIFO for clock domain crossing. FIFO's input clock is running at 61Mhz and output clock is running at 100Mhz. I'm passing the data from FIFO output to FFT core input. My FFT core is running at 100Mhz. Looking at your image above, it appears as though you have a much lower data rate than 100MHz. Can you tell me what your data rate is? Yes my data rate is 61MSPS. My FIFO outputs valid signal at the frequency of data rate so i connected this valid signal at FFT s_axis_data_tvalid signal. I also connected FFT out s_axis_data_tready to FIFO's m_axis_data_tready signal. You can see in screenshot that fft_s_axis_data_tready is asserted and util_fifo_m_axis_valid is toggling at the rate of 61MSPS. (ILA is running at 100Mhz) I notice that you are using a FIFO. Can you explain the purpose of this FIFO within your design? If the data rate going into the FFT is at 100MHz, then the FIFO really only makes sense if you have bursty data at a rate faster than 100MHz. I used the FIFO for clock domain crossing. Actually my data rate (61MSPS) is slower then my system clock(100Mhz). So if i lowered my system clock to 61Mhz, I would hurt my system's performance. Indeed, is your TLAST generation done at the rate of your incoming data? Or is your counter independent of incoming data samples? yes TLAST is being generated at incoming data rate (61Mhz). Here is how i'm calculating bins and indices. (Please correct me if i'm wrong.) My FFT size 65536 and FFT core is running at 100Mhz. So bin size -->100M/65536=1525.87890625Hz --Input 1Mhz signal expected index-->1M/1525.87890625 = 655 actual index = 1068 offset =413 --input 2Mhz expected index-->2Mhz/1525.87890625=1310 (2*655) actual index =2135 (2*1068) offset = 825 (2*413) This calculation shows that output has a fixed offset. I'm not using square root while calculating magnitude. My multipliers and adders are all combination so they won't add extra latency.
  5. Thanks for your answer .I will update this thread with all the required details by tomorrow
  6. I had inserted FFT core in a design after FIFO .at the output i am expecting a frequency bin on certain index but i am not getting the result.FFT core is working on 100mhz clock . Following steps i had implemented . - For FIFO to be work on 100 MHz, I verified this by sending the captured data to MATLAB and analyze DATA over there. So I received data correctly. - I inserted FFT core after ADC_FIFO in the reference design. That FIFO working correctly on 100MHz clock. But I didn’t get the correct DATA from the core. For verifying FFT core settings, I debugged FFT core with a DDS core. I mean generate a signal from DDS core and passed to FFT core, at the output I got correct result. So FFT core is also working fine s_axis_data_tdata[31:0] ( input [ real 16 bit , q 16 bit ] ) s_axis_data_tlast (I provide this signal from a counter which run upto FFT points) s_axis_data_tready [ output] s_axis_data_tvalid [coming from fifo] s_axis_config_tdata [ passed 0] s_axis_config_tready [ output] s_axis_config_tvalid [constant 1] m_axis_status_tready [constant 1] m_axis_data_tready [constant 1]
  7. Dear All I have bought NEXYS 4 recently . I have basic knowledge of VHDL . Now I want to go further in digital design system.Please suggest me some good books or video or guide me. I will be very thankful I have NEXYS 4 board and Xilinx 14.2 software installed on my PC.