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  1. Thank you for your quick response. My board clearly has some hardware problems. IC9 caught fire when I plugged the board in today, and the former input to IC9 is found to be short to input power (12V). I suspect regulator IC24 has failed. USB device has been successfully enumerated by shorting IC9 pin 1 to IC9 pin 5, and running off 5V USB in power.
  2. Good morning, I have spent many hours trying to get a working Arty Z7 board with USB Host capability. In particular, I would like to take input from a class-compliant MIDI device. I have created a Petalinux project from https://github.com/Digilent/Petalinux-Arty-Z7-20 repository using the following command: petalinux-create -t project -s /path/to/Petalinux-Arty-Z7-20-2017.4-1.bsp From here, I have simply loaded the pre-built images using a FAT32 SD card. I have plugged various devices (MIDI controller, Flash Drive) into the Arty Z7 USB Host port, none of which seem to be rec
  3. jpeyron, something must've gone wonky. This thread is still very much open debugasm, thank you for your answer! Unfortunately, the manual reset in the FSBL has not enabled USB by itself, nor in combination with the proposed device tree changes. Did you need to make any funky changes to the hardware platform? Also, might there be changes in the way Linux 4 deals with USB?
  4. Good afternoon! I am trying to get USB interfacing to work on the Zybo. Because I eventually want to build my own board, I am familiarizing myself with all parts of a functional toolchain. My toolchain looks like this: Generate hardware platform with Vivado 2016.2, using Digilent HW Platform Guide as a reference. Exporting hardware from Vivado. (Note: Hello World SDK project runs successfully from this HW design). Use Petalinux 2016.2 to create a project, load in files as necessary, and generate boot image, as described in UG1144. (Using hdf and bit generated with Vivado, FSBL
  5. As a dirty hack, you can change the applicable Vivado version in src/bd/system.tcl to 2016.2.
  6. Extremely helpful as usual, hamster! As you know, I'm working on a synth project. I'm gonna try the FIFO option with the producer (oscillator summer) operating at the 100MHz sysclock and the consumer feeding this to the DAC at 12.228.
  7. Evening, all. The code attempts to create a clock and synchronize it to sysclk. However, it fails timing analysis. `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Engineer: hamster, JUIXXXE ////////////////////////////////////////////////////////////////////////////////// module clk_div( input clk, output wire mclk, output wire bclk, output wire lrclk ); wire clkfb; reg [7:0] mclk_count = 0; MMCME2_BASE #( .BANDWIDTH("OPTIMIZED"), // Jitter programming (OPTIMIZED, HIGH, LOW)
  8. Note for future readers: Hamster and I have generated, in all likelihood, fully operational code. Hamster's VHDL code is explained here: http://hamsterworks.co.nz/mediawiki/index.php/PMODamp3 (down atm) My Verilog code is here: https://github.com/jcloiacon/synth And here is a video demonstration of mine: https://www.youtube.com/watch?v=zsd7MRDOyek
  9. Yes, JP6 was originally unloaded (supposedly corresponding to 0dB gain). Interestingly, loading JP6 eliminates most of the clipping, yielding the (still wonky) waveform attached below. I've been playing with the oscillator frequency, and the resultant waveform frequency varies predictably. Also, grounding the oscilloscope voids the signal for some reason? Also, what do you mean when you say "the speaker output needs to be slightly unseated"? IMG_002.BMP
  10. hamster, thank you for all your help! I've committed the project to Git at https://github.com/jcloiacon/synth . This is my first commit of this kind, so please lmk if I've screwed something up royally . I've made a few minor tweaks : firstly I've reduced the size of the sawtooth register to 16bits for simplicity. I've included the switch inputs so that they can be used later for demonstration / debugging. But I'm still not convinced this code works properly. I've scoped the output in parallel with my guitar amplifier load (8 ohms I think), and it still looks wonky. Image is attached. Anyways,
  11. Still no luck. Jumpers set as above. Here are my clock settings: mclk : 12.288 MHz bclk : 3.072 MHz (mclk/4) fs = lrclk: 48kHz (mclk / 256, tested with DSO Nano v3 Oscilloscope) sclk and lrclk synced to bclk falling edge The output is a noisy inverse saw, which peaks at about ±1.7V, which is probably the analog limit of the device (~3.3/2). The image is attached. Do you suspect there are problems with having a 12MHz signal on an output pin? My oscilloscope is too slow to check. IMG_007.BMP
  12. Nevermind, I got one using Vivado's Clocking Wizard IP.
  13. JColvin, thank you for your quick reply! It does seem that the SSM2518 requires specific sampling frequencies, a revelation which has shaken my understanding of the device as simply a clocked shift register attached to a DAC. That said -- and provided this is the case -- an accurate high frequency clock is now required, which precludes clocking by simple division of the available 100MHz clock. It seems that use of the clock management tiles (CMTs) is necessary. No chance you can point me to code which generates, for example, a 5.6448 MHz clock?
  14. Greetings all! I've been trying on and off since September to get a simple sawtooth to sound from the PMODAMP3, so that I can eventually make music with it. Here are my intended settings: JP5 unloaded: Standalone mode JP6 unloaded: 0dB gain JP3 loaded: i2s format JP4 loaded: MCLK = 256*fs JP2 loaded BCLK side. BCLK = fs*64 = MCLK/4 = 2.5MHz, therefore MCLK = 10MHz, fs = 39kHz I've attached the code in 4 Verilog files: Basys3_Abacus_Top.v (name inherited from example project), sclk_div.v (generates BCLK from FPGA clk), i2s_tx.v (i2s transmitter), and oscillator.v (produces a simple 1Hz sawtooth