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jcloiacon last won the day on January 25 2016

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  1. Good morning, I have spent many hours trying to get a working Arty Z7 board with USB Host capability. In particular, I would like to take input from a class-compliant MIDI device. I have created a Petalinux project from https://github.com/Digilent/Petalinux-Arty-Z7-20 repository using the following command: petalinux-create -t project -s /path/to/Petalinux-Arty-Z7-20-2017.4-1.bsp From here, I have simply loaded the pre-built images using a FAT32 SD card. I have plugged various devices (MIDI controller, Flash Drive) into the Arty Z7 USB Host port, none of which seem to be receiving power. "dmesg" output is not effected either. Here is the output of dmesg | grep -i "usb" : root@Arty-Z7-20:~# dmesg | grep -i "usb" usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver usbcore: registered new interface driver usb-storage e0002000.usb supply vbus not found, using dummy regulator Found TI TUSB1210 ULPI transceiver. ci_hdrc ci_hdrc.0: new USB bus registered, assigned bus number 1 ci_hdrc ci_hdrc.0: USB 2.0 started, EHCI 1.00 hub 1-0:1.0: USB hub found usbcore: registered new interface driver usbhid usbhid: USB HID core driver lsusb reveals the following: Bus 001 Device 001: ID 1d6b:0002 I suppose this is the onboard physical driver? The device tree, hardware description, and kernel options of this project seem like they should support USB host. I'm aware that on other Digilent devices, 5V power had to be forced. I am unable to rectify the voltages present on IC9 with what they should be per the Arty Z7 schematic. In fact, I can't find 5V anywhere on this board? How must the vanilla Petalinux project or board be modified to power and enumerate USB devices? TIA
  2. jcloiacon

    USB on Zybo

    jpeyron, something must've gone wonky. This thread is still very much open debugasm, thank you for your answer! Unfortunately, the manual reset in the FSBL has not enabled USB by itself, nor in combination with the proposed device tree changes. Did you need to make any funky changes to the hardware platform? Also, might there be changes in the way Linux 4 deals with USB?
  3. jcloiacon

    USB on Zybo

    Good afternoon! I am trying to get USB interfacing to work on the Zybo. Because I eventually want to build my own board, I am familiarizing myself with all parts of a functional toolchain. My toolchain looks like this: Generate hardware platform with Vivado 2016.2, using Digilent HW Platform Guide as a reference. Exporting hardware from Vivado. (Note: Hello World SDK project runs successfully from this HW design). Use Petalinux 2016.2 to create a project, load in files as necessary, and generate boot image, as described in UG1144. (Using hdf and bit generated with Vivado, FSBL and Device Tree unchanged from petalinux defaults) Copy BOOT.BIN and image.ub to SD card Linux boots properly, and I have shell access over UART. However, plugging and unplugging USB devices has no effect. By contrast, the prebuilt image provided in this Petalinux BSP repository based on the Digilent Linux BD can detect and identify USB peripherals. The default device tree and kernel configuration *look* complaint with the Zynq Linux USB Xilinx wiki page, with the exception that the device tree lines are divided between zynq-7000.dtsi and pcw.dtsi, and Generic ULPI Transceiver Driver is not an option when running petalinux-config -c kernel. Also, dmesg yields some information when run on the Zynq: root@julianzybo:~# dmesg | grep -i usb usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb ehci_hcd: USB 2.0 'Enhanced' Host Controller (EHCI) Driver usbcore: registered new interface driver usb-storage usbcore: registered new interface driver usbhid usbhid: USB HID core driver but lsusb isn't even present: root@julianzybo:~# lsusb -sh: lsusb: not found Has anyone successfully built Linux from a custom hardware platform, and gotten USB to work? EDIT: I have not connected any reset to USB0, but I do see the line usb-reset = <&gpio0 46 0>; in the Petalinux-BSP repository device tree. Perhaps a USB reset is necessary?
  4. jcloiacon

    Having trouble to generate a Project from digilent's Github

    As a dirty hack, you can change the applicable Vivado version in src/bd/system.tcl to 2016.2.
  5. jcloiacon

    Generate and Synchronizing Clock

    Extremely helpful as usual, hamster! As you know, I'm working on a synth project. I'm gonna try the FIFO option with the producer (oscillator summer) operating at the 100MHz sysclock and the consumer feeding this to the DAC at 12.228.
  6. jcloiacon

    Generate and Synchronizing Clock

    Evening, all. The code attempts to create a clock and synchronize it to sysclk. However, it fails timing analysis. `timescale 1ns / 1ps ////////////////////////////////////////////////////////////////////////////////// // Engineer: hamster, JUIXXXE ////////////////////////////////////////////////////////////////////////////////// module clk_div( input clk, output wire mclk, output wire bclk, output wire lrclk ); wire clkfb; reg [7:0] mclk_count = 0; MMCME2_BASE #( .BANDWIDTH("OPTIMIZED"), // Jitter programming (OPTIMIZED, HIGH, LOW) .CLKFBOUT_MULT_F(7.0), // Multiply value for all CLKOUT (2.000-64.000). .CLKFBOUT_PHASE(0.0), // Phase offset in degrees of CLKFB (-360.000-360.000). .CLKIN1_PERIOD(10.0), // Input clock period in ns to ps resolution (i.e. 33.333 is 30 MHz). // CLKOUT0_DIVIDE - CLKOUT6_DIVIDE: Divide amount for each CLKOUT (1-128) .CLKOUT0_DIVIDE_F(57.0), // Divide amount for CLKOUT0 (1.000-128.000). .CLKOUT1_DIVIDE(14), .CLKOUT2_DIVIDE(14), .CLKOUT3_DIVIDE(14), .CLKOUT4_DIVIDE(14), .CLKOUT5_DIVIDE(14), .CLKOUT6_DIVIDE(14), // CLKOUT0_DUTY_CYCLE - CLKOUT6_DUTY_CYCLE: Duty cycle for each CLKOUT (0.01-0.99). .CLKOUT0_DUTY_CYCLE(0.5), .CLKOUT1_DUTY_CYCLE(0.5), .CLKOUT2_DUTY_CYCLE(0.5), .CLKOUT3_DUTY_CYCLE(0.5), .CLKOUT4_DUTY_CYCLE(0.5), .CLKOUT5_DUTY_CYCLE(0.5), .CLKOUT6_DUTY_CYCLE(0.5), // CLKOUT0_PHASE - CLKOUT6_PHASE: Phase offset for each CLKOUT (-360.000-360.000). .CLKOUT0_PHASE(0.0), .CLKOUT1_PHASE(0.0), .CLKOUT2_PHASE(0.0), .CLKOUT3_PHASE(0.0), .CLKOUT4_PHASE(0.0), .CLKOUT5_PHASE(0.0), .CLKOUT6_PHASE(0.0), .CLKOUT4_CASCADE("FALSE"), // Cascade CLKOUT4 counter with CLKOUT6 (FALSE, TRUE) .DIVCLK_DIVIDE(1), // Master division value (1-106) .REF_JITTER1(0.0), // Reference input jitter in UI (0.000-0.999). .STARTUP_WAIT("FALSE") // Delays DONE until MMCM is locked (FALSE, TRUE) ) MMCME2_BASE_inst ( // Clock Outputs: 1-bit (each) output: User configurable clock outputs .CLKOUT0(mclk), // 1-bit output: CLKOUT0 .CLKOUT0B(CLKOUT0B), // 1-bit output: Inverted CLKOUT0 .CLKOUT1(CLKOUT1), // 1-bit output: CLKOUT1 .CLKOUT1B(CLKOUT1B), // 1-bit output: Inverted CLKOUT1 .CLKOUT2(CLKOUT2), // 1-bit output: CLKOUT2 .CLKOUT2B(CLKOUT2B), // 1-bit output: Inverted CLKOUT2 .CLKOUT3(CLKOUT3), // 1-bit output: CLKOUT3 .CLKOUT3B(CLKOUT3B), // 1-bit output: Inverted CLKOUT3 .CLKOUT4(CLKOUT4), // 1-bit output: CLKOUT4 .CLKOUT5(CLKOUT5), // 1-bit output: CLKOUT5 .CLKOUT6(CLKOUT6), // 1-bit output: CLKOUT6 // Feedback Clocks: 1-bit (each) output: Clock feedback ports .CLKFBOUT(clkfb), // 1-bit output: Feedback clock .CLKFBOUTB(CLKFBOUTB), // 1-bit output: Inverted CLKFBOUT // Status Ports: 1-bit (each) output: MMCM status ports .LOCKED(LOCKED), // 1-bit output: LOCK // Clock Inputs: 1-bit (each) input: Clock input .CLKIN1(clk), // 1-bit input: Clock // Control Ports: 1-bit (each) input: MMCM control ports .PWRDWN(1'b0), // 1-bit input: Power-down .RST(1'b0), // 1-bit input: Reset // Feedback Clocks: 1-bit (each) input: Clock feedback ports .CLKFBIN(clkfb) // 1-bit input: Feedback clock ); assign bclk = mclk_count[2]; // mclk / 8 assign lrclk = mclk_count[7]; // mclk / 256 reg mclk_last; always@(posedge(clk)) begin if(mclk & !mclk_last) mclk_count <= mclk_count + 1; mclk_last <= mclk; end endmodule From CLKOUT0 to mclk_count fails timing analysis. How can the code be restructured to avoid this?
  7. jcloiacon

    PMODAMP3 in Verilog with Basys 3

    Note for future readers: Hamster and I have generated, in all likelihood, fully operational code. Hamster's VHDL code is explained here: http://hamsterworks.co.nz/mediawiki/index.php/PMODamp3 (down atm) My Verilog code is here: https://github.com/jcloiacon/synth And here is a video demonstration of mine: https://www.youtube.com/watch?v=zsd7MRDOyek
  8. jcloiacon

    PMODAMP3 in Verilog with Basys 3

    Yes, JP6 was originally unloaded (supposedly corresponding to 0dB gain). Interestingly, loading JP6 eliminates most of the clipping, yielding the (still wonky) waveform attached below. I've been playing with the oscillator frequency, and the resultant waveform frequency varies predictably. Also, grounding the oscilloscope voids the signal for some reason? Also, what do you mean when you say "the speaker output needs to be slightly unseated"? IMG_002.BMP
  9. jcloiacon

    PMODAMP3 in Verilog with Basys 3

    hamster, thank you for all your help! I've committed the project to Git at https://github.com/jcloiacon/synth . This is my first commit of this kind, so please lmk if I've screwed something up royally . I've made a few minor tweaks : firstly I've reduced the size of the sawtooth register to 16bits for simplicity. I've included the switch inputs so that they can be used later for demonstration / debugging. But I'm still not convinced this code works properly. I've scoped the output in parallel with my guitar amplifier load (8 ohms I think), and it still looks wonky. Image is attached. Anyways, I'm dying to get this thing to work. I feel that we are very close. May I invite you to edit the Git? IMG_003.BMP
  10. jcloiacon

    PMODAMP3 in Verilog with Basys 3

    Still no luck. Jumpers set as above. Here are my clock settings: mclk : 12.288 MHz bclk : 3.072 MHz (mclk/4) fs = lrclk: 48kHz (mclk / 256, tested with DSO Nano v3 Oscilloscope) sclk and lrclk synced to bclk falling edge The output is a noisy inverse saw, which peaks at about ±1.7V, which is probably the analog limit of the device (~3.3/2). The image is attached. Do you suspect there are problems with having a 12MHz signal on an output pin? My oscilloscope is too slow to check. IMG_007.BMP
  11. jcloiacon

    PMODAMP3 in Verilog with Basys 3

    Nevermind, I got one using Vivado's Clocking Wizard IP.
  12. jcloiacon

    PMODAMP3 in Verilog with Basys 3

    JColvin, thank you for your quick reply! It does seem that the SSM2518 requires specific sampling frequencies, a revelation which has shaken my understanding of the device as simply a clocked shift register attached to a DAC. That said -- and provided this is the case -- an accurate high frequency clock is now required, which precludes clocking by simple division of the available 100MHz clock. It seems that use of the clock management tiles (CMTs) is necessary. No chance you can point me to code which generates, for example, a 5.6448 MHz clock?
  13. jcloiacon

    PMODAMP3 in Verilog with Basys 3

    Greetings all! I've been trying on and off since September to get a simple sawtooth to sound from the PMODAMP3, so that I can eventually make music with it. Here are my intended settings: JP5 unloaded: Standalone mode JP6 unloaded: 0dB gain JP3 loaded: i2s format JP4 loaded: MCLK = 256*fs JP2 loaded BCLK side. BCLK = fs*64 = MCLK/4 = 2.5MHz, therefore MCLK = 10MHz, fs = 39kHz I've attached the code in 4 Verilog files: Basys3_Abacus_Top.v (name inherited from example project), sclk_div.v (generates BCLK from FPGA clk), i2s_tx.v (i2s transmitter), and oscillator.v (produces a simple 1Hz sawtooth), as well as test benches for i2s_tx and Basys3_Abacus_top. All of these files are relatively simple. In addition, I've attached the constraint file, and an image of the output, taken with my DSO NANO V3. Furthermore, I've zipped up the entire project and uploaded here: https://drive.google.com/file/d/0B_8d0gTEx0yqaDFyOUhCTGU0QW8/view?usp=sharing Some thoughts: Maybe SSM2518 doesn't know to generate MCLK as 4xBCLK? Faulty chip? Anyways, if one of you has the time and energy to either point out flaws in my verilog or hardware setup, I would be very grateful. TIA oscillator.v i2s_tx.v sclk_div.v i2stx_tb.v Basys3_Master.xdc Basys3_Abacus_Top.v IMG_001.BMP