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  1. I purchased a Nexys-Video and implemented a Microblaze based project on it by following a tutorial on Digilent's website https://reference.digilentinc.com/nexys-video:gsmb?do= Before I started I made sure I got the latest set of board files from the digilent website. I followed the instructions as indicated, although I noticed that there were some inconsistencies in the tutorial as in some screens hinted that the tutorial was written originally for the Nexys4DDR and was later adapted for the Nexys-Video board (some screens still show Nexys4DDR). I tried pasting here a picture of the the system I obtained at the end but this website would not let me. Any way, my system matches exactly the one in the tutorial. The validation passed, synthesis also passed ( although it gave me the same error the tutorial asked me to ignore, which I did). However, before running implementation I ran a "Report Timing Summary" from the Synthesized Design sub-menu, It gave me the several errors related to the oserdes_clk... To make sure these errors were not caused by something I may have entered wrong while creating the project, I decided to re-do the project starting from a blank slate, but the results were exactly the same in the new project. I tried to paste here an image with the errors but this website would not let me .... Anyway, the errors were Inter-clock paths / oserdes_clk to oserdes_clk / Hold -0.246ns (10 occurrences) Below is one of the Interclock paths that had the Hold timing error From: main_bd_i/mig_7series_0/u_main_bd_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out/OCLK To: main_bd_i/mig_7series_0/u_main_bd_mig_7series_0_1_mig/u_memc_ui_top_axi/mem_intfc0/ddr_phy_top0/u_ddr_mc_phy_wrapper/u_ddr_mc_phy/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/output_[6].oserdes_dq_.sdr.oserdes_dq_i/RST I think the error is due to a lack of one or more timing constraints. I suspect there might be an error with the board files associated to the Nexys-Video board, specifically related to the MIG7 and the DDR . I do not have enough knowledge of the system to be able to make the constraints myself. How could I solve these timing errors? Thanks
  2. Hi Sbobrowicz, I understand that the PMOD connectors may not be high speed (due to their impedance). Do you know of any other connector I could adapt to my Arty to make it high speed? I need to run signals at about 100MHz... Hopefully I can include a circuit to make the translation from TMDS_33 to LVDS 2.5V Thanks
  3. I do have the same problem... This problem should be notified to Xilinx Vivado developers ...
  4. Hi Sbobrowicz, Do you think that another option to solve this LVDS voltage configurability issue may be to move from the ARTY to the NEXYS VIDEO ARTIX-7 FPGA-trainer board...This board seems to have selectability for the port banks' voltage... Thanks
  5. HI, I have a situation in which I have to interface my ARTY with an ADC evaluation board that uses only LVDS (2 inputs, 2 outputs). In the message above you mention that one could use for High-Speed differential Output the TMDS_33 IOSTANDARD. Is this a setting I have to specify in my Vivado project? Thanks
  6. Good day, I need to interface an ARTY board to an ADC evaluation board from Analog Devices (EVAL-AD7626/25FMCZ). This ADC board only interfaces via LVDS but I understand the ARTY does not have any ports with this standard. I need your advice in how to best approach this problem. I need to connect 4 pairs of LVDS signals to the ARTY, 2 pairs will be inputs and the other two will be outputs. At this time I am planning to make a PCB to interconnect these two boards (on one end this PCB will connect with the ARTY's high-speed PMODs, on the other it will connect with the ADC board's FMC connector. I plan to include LVDS drivers (i.e. an external IC) to connect the ADC inputs to the Arty's outputs. Now, for the connection between the ADC LVDS outputs to the ARTY's inputs I understand that I may be able via the PMOD high-speed differential inputs. Is this correct? In this case I would not know if I need to install a resistor between each differential input pair to comply with the LVDS standard... I will appreciate your comments about the idea above and also on any advice on how to connect the ARTY's PMODs HighSpeed differential outputs to the LVDS drivers. Thanks
  7. Hi, I am implementing in Vivado the Arty's Microblaze based design that Adam Taylor posted on his website: http://adiuvoengineering.com/?p=626I I am having problems with it: Synthesis ran without any high importance warnings, but at the end of implementation I get three high severity warnings after I run the "Report Timing Summary": USB_UART_RXD: Port with no Input DelayUSB_UART_TXD: Port with no Input Delayddr3_sdram_reset_n: Port with no Output DelayI do not know how should I constrain these inputs and outputs. (Note: My Arty environment is working ok (board files have been downloaded and installed). I already have ran some basic logic circuits in the ARTY board successfully. My problems started with this project that includes the Microblaze and the uart) Attached are the snapshot of my block design (It is basically a copy of Adam Taylor's design) and a copy of the warnings I get. Let me know if I need to do something about these warnings, and if so, how, Thanks!
  8. The problem was that I needed to include the "board files" for the Arty in the Vivado directory... Installing the software was a bit confusing for me... There are no clear instructions on the Digilent website at least I did not see them. I think Digilent could do a better job with its website navigability. Xilinx just guides you to install Vivado, but it does not care about the board that one is using... If one is getting a license locked for a particular board, the least they could do was to include all the board files automatically in the installation... There is a very good website (from an enthusiast) with information on how to install Vivado to be used with Arty http://eb.dy.fi/2015/11/installing-vivado-for-arty/ . The same website has tutorial and basic "Hello World" projects that are clearly and neatly described... Digilent or Xilinx should have links to his website.. http://eb.dy.fi/2015/11/arty-hello-world/#comment-7266
  9. Good day, I just bought an ARTY board and it came with the "Artix-7 35T Evaluation Kit and Tools Voucher". I believe I have a problem with the Vivado as apparently the Arty board was not properly included in the Vivado setup... After I got my voucher for Vivado I downloaded and installed it on my computer. I ran the software and Vivado and connected the board to the USB port. Then I opened the Hardware manager and only after I clicked on "AutoConnect" Vivado recognized the board: On the Hardware list there appeared a Xilinx_tcf/.../xc7a35T-0/XADC (see the attached image Vivado Screenshot #1)... So far it identifies the FPGA of the board... I tried running the "Out-Of-Box GPIO Example Design for the Arty Evaluation Board" that I downloaded from http://www.xilinx.com/products/boards-and-kits/arty.html#documentation I followed the instructions but could not run the batch files as apparently the "XILINX_VIVADO" env variable had not been set... Then I found a "Hello World" program at http://eb.dy.fi/2015/11/arty-hello-world/ which is very well explained and wanted to use it to get started with something with the Arty... I followed the steps but got stuck at the moment of choosing the Default Part... Vivado gives us the option of choosing a board and presents a list of boards to select from it... in the tutorial I was following there appeared the "Arty" and the "Artix-7 AC701 Evaluation Platform" boards (see the SCREENSHOT FROM TUTORIAL attached)... However when I try to select the board my Vivado shows a longer list but the "Arty" is not included... (See the Vivado Screenshot #2 attached) In this list there appears the "Artix-7 AC701 Evaluation Platform" but I do not think I should select it as it is a different board (even though they have the same FPGA) I look forward to hear your comments to solve this issue and be able to work with Vivado and my Arty Thanks Jesse ------ VIVADO SCREENSHOT #1 SCREENSHOT FROM TUTORIAL VIVADO SCREENSHOT #2