Twoism

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  1. Twoism

    Zybo base system design

    Hello, I've got some troubles while trying to fully understand the Zybo base system design. I need to replicate in my design (with Vivado 2015.4) the video part of the bsd, with the Axi display control ip. The design works but some points are not very clear to me: I've notice that 2 different clock sources are feed to the PL: (FCLK_CLK0 @ 100 MHz and FCLK_CLK1 @ 150 MHz). What is the reason behind this? Isn't 100 MHz enough for the VDMA? Why an Axi protocol converter is used? The design was build for an older version of Vivado (and ip library)? Thanks
  2. Hi, I'm not able to fully understand the relation between the Board file and the Constraints file in Vivado. In my design I need to connect a custom IP block to a Pmod connector on a ZYBO board. I've loaded the XML board file provided by Digilent but now I'm not anymore able to customize the pins as i would do with a constraint file since it seem to me that the mapping it is now specified in the XML file. # Pmod connector JB set_property PACKAGE_PIN T20 [get_ports {d_out[0]}] set_property PACKAGE_PIN U20 [get_ports {d_out[1]}] set_property PACKAGE_PIN V20 [get_ports {d_out[2]}] set_property PACKAGE_PIN W20 [get_ports {d_out[3]}] set_property IOSTANDARD LVCMOS33 [get_ports {d_out[*]}]Should I need to add a constraint file even if the Board port mapping is already specified by the board file? Is this a good practice? Thanks