Anding

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Anding last won the day on January 7 2016

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  1. Anding

    HDMI on the Nexys4-DDR?

    What a great idea! Thank you Dan, I was not aware of it.
  2. Anding

    HDMI on the Nexys4-DDR?

    Hello, Is there any way that I can connect the Nexys4DDR to an HDMI connector, for example using a breakout board such as this one https://www.adafruit.com/product/3119 The critical factor would be getting access to 4 differential pair outputs (TMDS) from the Artix-7 FPGA. I note that there is no HDMI PMOD available, which suggests that these pins are actually not available externally on this board. I already have the Nexys4DDR, which is the right board for me. I don't need the dedicated Nexys Video, I'm just trying to upgrade my display output from VGA to HDMI - which could be a relatively simple job. Related to this, if I can post my request for the next version of the Nexys4 board: replace the VGA connector with a DVI connector and connect both the "VGA" pins and the "HDMI" pins from the DVI connector to the FPGA. Users can then either uses a DVI/HDMI cable or an DVI/VGA adaptor at preference.
  3. Thank you jpeyron, I'll post again after I try those settings.
  4. DRC CFGBVS-1 Missing CFGBVS and CONFIG_VOLTAGE Design Properties: Neither the CFGBVS nor CONFIG_VOLTAGE voltage property is set in the current_design. Configuration bank voltage select (CFGBVS) must be set to VCCO or GND, and CONFIG_VOLTAGE must be set to the correct configuration voltage, in order to determine the I/O voltage support for the pins in bank 0. It is suggested to specify these either using the 'Edit Device Properties' function in the GUI or directly in the XDC file using the following syntax: set_property CFGBVS value1 [current_design] #where value1 is either VCCO or GND set_property CONFIG_VOLTAGE value2 [current_design] #where value2 is the voltage provided to configuration bank 0 Refer to the device configuration user guide for more information. For the Nexys4DDR 1) should I use VCCO or GND for CFGBVS? 2) What is the value I should use for CONFIG_VLOTAGE Once I have this information I can set the properties in the XDC file. I know I could just ignore the warnings but that's a distraction, so I'd prefer to just complete the XDC file properly. Many thanks,
  5. Hi Marshall, Yes, ISE will work fine in Windows 10 with that same rename-the-lib-files fix as Windows 7/8. Thank you for the suggestion on the SRAM to DDR component. I found reviewing the code very instructive. But of course that component also relies on instantiating a MIG if it is to run in hardware. For my own project I have been able to write a small module to interface directly with the MIG's user interface and which will give me a burst mode and has some arbitration for multiple ports. It simulates successfully, but igetting the MIG itself through place and route which has been the difficulty! Thanks again for all of your suggestion. I'm sure I'll be posting here again.
  6. Hi Marshall, Andrew Thank you very much for your post. I believe you are right that spending too much time with MIG in ISE is not really productive. I've actually migrated my project to Vivado as a standby but after a couple of months my personal view is that, apart from the MIG issue, ISE is still a nicer tool for a hobbiest the like myself. I'll cite some examples: Vivado doesn't actually support Windows 10 - wizard file dialogs simply crash out (including the MIG wizard!). ISE works fine in Windows 10 with a simple fix Its easy to create instantiation templates and testbenches with a "right-click" in ISE, but the TCL tools in Vivado don't work especially well Vivado doesn't recognise the VHDL method of instantiating entities without a prior component declaration (inst: entity work.EntityName), so either you create (and continually modify) component declarations for all entities or use a ugly workaround by setting all files as global includes. The Vivado simulator is much faster when it is running but takes a lot longer to get started than ISE, so not so good for rapid iteration and testing SmartXplorer is very helpful in closing timing, but it's gone in Vivado The other option is to manage without the MIG and develop a DDR2 interface in VHDL. How feasible would you judge that this is? thanks again, Anding
  7. Hello does Diligent have the specifications to be used with the Vivado TCL command write_cfgmem to create a Nexys4 .mcs file, please?
  8. Thank you for the responses. I really look forward to any example that you may be able to share
  9. Hello, I've asked a few separate questions about getting implementing the Xilinx MIG on the Nexys4DDR using ISE 14.7. Unfortunately I am still struggling with it. I wondered is there anyone, perhaps at Digilent or elsewhere, who has successfully implemented MIG in a Nexys4DDR design using ISE? If you have, would it be possible for me to take a look at the code where you instantiate the MIG and the (final and likely modified) MIG-generated timing constraints file that you are using? This would really be a great kindness. Question to Digilent here: I notice that all of your Nexys4DDR projects that use the DDR memory were migrated to Vivado before being released. Is the implication here that a Nexys4DDR design using MIG in ISE, is really not feasible? I'd much appreciate any responses : so I can either get inspiration from your successful code (which would be greatly appreciated :-) or acknowledge defeat in ISE and at least stop losing time on this issue. Many thanks
  10. Hello JColvin, May I ask for something that would help me a lot? If you colleagues have an ISE project for the Nexys4DDR that includes a MIG and which has been successfully implemented in hardware, would it be possible to get a copy of the .UCF file with the timing constraints that the MIG generated? It is found inside the MIG IP folder. (I don't mean the simple .UCF file that has the pin outs only; that is already on your website) I could compare this known good version with what the MIGis generating in my design. The engineers may actually have take the automatically-generated .UCF file and modified it to get the MIG to work. A copy of that modified file would be especially valuable! Many thanks indeed,
  11. Hello, I'm having trouble getting place and route (ISE) to meet timing on the Nexys4DDR. The design is an update of an original design on the Nexys4 which met timing easily. The only change is that a MIG7 has been substituted for the previous cellularRAM controller. If it's not bad form and to avoid duplicate posts, may I link to where I have posted the issue on the Xilinx forum... https://forums.xilinx.com/t5/Memory-Interfaces/MIG7-Unusually-high-hold-time-violation-detected/m-p/679727 Many thanks indeed for any suggestions
  12. Anding

    Map problem on Nexys4DDR

    "File upload failed". UCF file pasted here ################################################################################################## ## ## Xilinx, Inc. 2010 www.xilinx.com ## Tue 26. Jan 16:28:58 2016 ## Generated by MIG Version 1.9 ## ################################################################################################## ## File name : MIG7.ucf ## Details : Constraints file ## FPGA Family: ARTIX7 ## FPGA Part: XC7A100T-CSG324 ## Speedgrade: -3 ## Design Entry: VHDL ## Frequency: 400 MHz ## Time Period: 2500 ps ################################################################################################## ################################################################################################## ## Controller 0 ## Memory Device: DDR2_SDRAM->Components->MT47H64M16HR-25E ## Data Width: 16 ## Time Period: 2500 ## Data Mask: 1 ################################################################################################## #NET "sys_clk_i" TNM_NET = TNM_sys_clk; #TIMESPEC "TS_sys_clk" = PERIOD "TNM_sys_clk" 5 ns; ############## NET - IOSTANDARD ################## NET "ddr2_dq[0]" LOC = "R7" | IOSTANDARD = SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L23P_T3_34 NET "ddr2_dq[1]" LOC = "V6" | IOSTANDARD = SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L20N_T3_34 NET "ddr2_dq[2]" LOC = "R8" | IOSTANDARD = SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L24P_T3_34 NET "ddr2_dq[3]" LOC = "U7" | IOSTANDARD = SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L22P_T3_34 NET "ddr2_dq[4]" LOC = "V7" | IOSTANDARD = SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L20P_T3_34 NET "ddr2_dq[5]" LOC = "R6" | IOSTANDARD = SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L19P_T3_34 NET "ddr2_dq[6]" LOC = "U6" | IOSTANDARD = SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L22N_T3_34 NET "ddr2_dq[7]" LOC = "R5" | IOSTANDARD = SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L19N_T3_VREF_34 NET "ddr2_dq[8]" LOC = "T5" | IOSTANDARD = SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L12P_T1_MRCC_34 NET "ddr2_dq[9]" LOC = "U3" | IOSTANDARD = SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L8N_T1_34 NET "ddr2_dq[10]" LOC = "V5" | IOSTANDARD = SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L10P_T1_34 NET "ddr2_dq[11]" LOC = "U4" | IOSTANDARD = SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L8P_T1_34 NET "ddr2_dq[12]" LOC = "V4" | IOSTANDARD = SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L10N_T1_34 NET "ddr2_dq[13]" LOC = "T4" | IOSTANDARD = SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L12N_T1_MRCC_34 NET "ddr2_dq[14]" LOC = "V1" | IOSTANDARD = SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L7N_T1_34 NET "ddr2_dq[15]" LOC = "T3" | IOSTANDARD = SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L11N_T1_SRCC_34 NET "ddr2_addr[12]" LOC = "N6" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L18N_T2_34 NET "ddr2_addr[11]" LOC = "K5" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L5P_T0_34 NET "ddr2_addr[10]" LOC = "R2" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L15N_T2_DQS_34 NET "ddr2_addr[9]" LOC = "N5" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L13P_T2_MRCC_34 NET "ddr2_addr[8]" LOC = "L4" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L5N_T0_34 NET "ddr2_addr[7]" LOC = "N1" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L3N_T0_DQS_34 NET "ddr2_addr[6]" LOC = "M2" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L4N_T0_34 NET "ddr2_addr[5]" LOC = "P5" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L13N_T2_MRCC_34 NET "ddr2_addr[4]" LOC = "L3" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L2N_T0_34 NET "ddr2_addr[3]" LOC = "T1" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L17N_T2_34 NET "ddr2_addr[2]" LOC = "M6" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L18P_T2_34 NET "ddr2_addr[1]" LOC = "P4" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L14P_T2_SRCC_34 NET "ddr2_addr[0]" LOC = "M4" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L16P_T2_34 NET "ddr2_ba[2]" LOC = "R1" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L17P_T2_34 NET "ddr2_ba[1]" LOC = "P3" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L14N_T2_SRCC_34 NET "ddr2_ba[0]" LOC = "P2" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L15P_T2_DQS_34 NET "ddr2_ras_n" LOC = "N4" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L16N_T2_34 NET "ddr2_cas_n" LOC = "L1" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L1P_T0_34 NET "ddr2_we_n" LOC = "N2" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L3P_T0_DQS_34 NET "ddr2_cke[0]" LOC = "M1" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L1N_T0_34 NET "ddr2_odt[0]" LOC = "M3" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L4P_T0_34 NET "ddr2_cs_n[0]" LOC = "K6" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_0_34 NET "ddr2_dm[0]" LOC = "T6" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L23N_T3_34 NET "ddr2_dm[1]" LOC = "U1" | IOSTANDARD = SSTL18_II | SLEW = FAST ; # Pad function: IO_L7P_T1_34 NET "ddr2_dqs_p[0]" LOC = "U9" | IOSTANDARD = DIFF_SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L21P_T3_DQS_34 NET "ddr2_dqs_n[0]" LOC = "V9" | IOSTANDARD = DIFF_SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L21N_T3_DQS_34 NET "ddr2_dqs_p[1]" LOC = "U2" | IOSTANDARD = DIFF_SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L9P_T1_DQS_34 NET "ddr2_dqs_n[1]" LOC = "V2" | IOSTANDARD = DIFF_SSTL18_II | SLEW = FAST | IN_TERM = UNTUNED_SPLIT_50 ; # Pad function: IO_L9N_T1_DQS_34 NET "ddr2_ck_p[0]" LOC = "L6" | IOSTANDARD = DIFF_SSTL18_II | SLEW = FAST ; # Pad function: IO_L6P_T0_34 NET "ddr2_ck_n[0]" LOC = "L5" | IOSTANDARD = DIFF_SSTL18_II | SLEW = FAST ; # Pad function: IO_L6N_T0_VREF_34 CONFIG INTERNAL_VREF_BANK34= 0.900; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_out" LOC=PHASER_OUT_PHY_X1Y7; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_out" LOC=PHASER_OUT_PHY_X1Y5; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_out" LOC=PHASER_OUT_PHY_X1Y6; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_out" LOC=PHASER_OUT_PHY_X1Y4; ## INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y7; ## INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y5; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y6; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/phaser_in_gen.phaser_in" LOC=PHASER_IN_PHY_X1Y4; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_D.ddr_byte_lane_D/out_fifo" LOC=OUT_FIFO_X1Y7; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_B.ddr_byte_lane_B/out_fifo" LOC=OUT_FIFO_X1Y5; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/out_fifo" LOC=OUT_FIFO_X1Y6; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/out_fifo" LOC=OUT_FIFO_X1Y4; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y6; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/in_fifo_gen.in_fifo" LOC=IN_FIFO_X1Y4; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phy_control_i" LOC=PHY_CONTROL_X1Y1; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/phaser_ref_i" LOC=PHASER_REF_X1Y1; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_C.ddr_byte_lane_C/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y81; INST "*/ddr_phy_4lanes_0.u_ddr_phy_4lanes/ddr_byte_lane_A.ddr_byte_lane_A/ddr_byte_group_io/*slave_ts" LOC=OLOGIC_X1Y57; INST "*/u_ddr2_infrastructure/plle2_i" LOC=PLLE2_ADV_X1Y1; INST "*/u_ddr2_infrastructure/gen_mmcm.mmcm_i" LOC=MMCME2_ADV_X1Y1; NET "*/iserdes_clk" TNM_NET = "TNM_ISERDES_CLK"; INST "*/mc0/mc_read_idle_r" TNM = "TNM_SOURCE_IDLE"; INST "*/input_[?].iserdes_dq_.iserdesdq" TNM = "TNM_DEST_ISERDES"; TIMESPEC "TS_ISERDES_CLOCK" = PERIOD "TNM_ISERDES_CLK" 2500 ps; TIMESPEC TS_MULTICYCLEPATH = FROM "TNM_SOURCE_IDLE" TO "TNM_DEST_ISERDES" TS_ISERDES_CLOCK*6; INST "*/device_temp_sync_r1*" TNM="TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC"; TIMESPEC "TS_MULTICYCLEPATH_DEVICE_TEMP_SYNC" = TO "TNM_MULTICYCLEPATH_DEVICE_TEMP_SYNC" 20 ns DATAPATHONLY;
  13. Anding

    Map problem on Nexys4DDR

    Hello, I made some further progress since my posting. I was not aware of it, but the MIG core generator in ISE creates it's own .UCF file in the ipcore_dir/NAME/user_design/constraints folder. MAP needs to read this file to locate the vref, etc.. However per this answer record sometimes ISE sometimes fails to recognize this UCF file. http://www.xilinx.com/support/answers/36427.html The workaround is to copy and rename this file, then manually include it in the project. I also needed to change the relative paths on two of the INST items by adding "*/" as a prefix INST "*/u_ddr2_infrastructure/plle2_i" LOC=PLLE2_ADV_X1Y1; INST "*/u_ddr2_infrastructure/gen_mmcm.mmcm_i" LOC=MMCME2_ADV_X1Y1; With these adjustments MAP has completed OK. I have attached my revised UCF file here. I wonder if someone familiar with MIG would mind having a quick look and offer feedback on any obvious issues or whether this sounds like the correct approach? Many thanks,
  14. Anding

    Map problem on Nexys4DDR

    Hi Andrew, Thank you for these suggestions. I double checked that Internal Vref is enabled and removed mig.ucf from my project. I now get the following MAP error. Please see also an image of the MIG instantiation dialog. Your further advice would be much appreciated: ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<2>. The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18. ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<1>. The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18. ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<4>. The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18. ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<3>. The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18. ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<15>. The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18. ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<0>. The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18. ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<9>. The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18. ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<6>. The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18. ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<5>. The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18. ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<8>. The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18. ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<7>. The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18. ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<10>. The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18. ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<11>. The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18. ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<12>. The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18. ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<13>. The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18. ERROR:PhysDesignRules:2407 - Unsupported IO configuration for comp ddr2_dq<14>. The use of input pin IBUFDISABLE is not compatible with IO standard LVCMOS18. ERROR:Pack:1642 - Errors in physical DRC.
  15. Anding

    Map problem on Nexys4DDR

    Thank you Bobby. I'm looking forward to hearing from your team.