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Andrew Catalano

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  1. Hello! I am still new to all of this so bare with me. I am creating a project that involves the JSTK2 PMOD and right now I want to test the PMOD on its own with the example codes on the Diligent GitHub before integrating to my system. However, I am getting stuck at generating a bitstream. I have already done this successfully in another RTL project with the KYPD PMOD and there were no problems. I will share a screenshot of my block design. I am using the Zybo Z7-10 and I am using Vivado 2021.1. I used this link to help me get started with my IP: https://digilent.com/reference/learn/programmable-logic/tutorials/pmod-ips/start Like I mentioned this worked for the KYPD PMOD. Let me know if anything else is needed to help debug this. Here are the error messages: [DRC NSTD-1] Unspecified I/O Standard: 4 out of 138 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Pmod_out_0_pin10_io, Pmod_out_0_pin7_io, Pmod_out_0_pin8_io, and Pmod_out_0_pin9_io. [DRC UCIO-1] Unconstrained Logical Port: 4 out of 138 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: Pmod_out_0_pin10_io, Pmod_out_0_pin7_io, Pmod_out_0_pin8_io, and Pmod_out_0_pin9_io. My assumption is that my constraints aren't defined properly but I am not sure where to go from there. Any advice/help would be greatly appreciated. Thank you!
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