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Jason3_14

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Everything posted by Jason3_14

  1. Hi, I am trying to do secure boot on the GenesysZU3G. The following is a comment in fsbl_%.bbappend for the OOB image: # Exclude Secure feature from FSBL until -O2 compilation bug is fixed YAML_COMPILER_FLAGS_append = " -DFSBL_SECURE_EXCLUDE" YAML_COMPILER_FLAGS_append = " -DUHS_MODE_ENABLE" YAML_COMPILER_FLAGS_append = " -DXPS_BOARD_GZU_3EG" Was this issue ever resolved? I tried removing the FSBL_SECURE_EXCLUDE, but I get build errors. If I build the fsbl locally using Vitis 2020.1 with FSBL_SECURE enabled, everything boots fine but the kernel hangs. Although it looks like a device tree issue, I don't think it is because if I replace the FSBL I built with Vitis 2020.1 with the one that builds with the OOB, it boots to the command prompt and doesn't hang. The so issue is definitely being caused by the FSBL.
  2. I am using Vitis 2020.1 with the on-board USB/JTAG programmer. I just connect the USB cable directly to the board from the Host machine.
  3. Hi, I tried the project zip from the repository with Vitis 2020.1 https://github.com/Digilent/Genesys-ZU/releases/tag/3EG%2FHELLO-WORLD%2F2020.1-1. I get the same error. It looks like the debugger is downloading to the wrong location. Its starting at address 0. I rebooted my host machine before trying to connect and power cycled the Genesys.
  4. Hi, I am following the steps from the following tutorial: https://digilent.com/reference/programmable-logic/guides/getting-started-with-ipi When I try to load the application with the debugger, I get the following error: xsct% Info: Cortex-A53 #0 (target 9) Stopped at 0x0 (Cannot resume. Cannot read 'pc'. Cannot read 'r0'. Cortex-A53 #0: EDITR not ready) I am using Vitis 2020.2 and Vivado 2020.2. There is no PL in the design. I have the PL-PS interface disabled. Its just a basic Hello World. The target is Genesys ZU 3eg Rev. D I used both the board file and constraints file from the Digilent repository. How do I load, run, and debug the application over JTAG? regards, Jason I think there might be a problem with the Block Automation in the Genesys Zu 3eg file. After running Block Automation the Address Editor is blank.
  5. Hi, Thanks for the reply. I don't need a prebuilt image. I need to be able to build the image myself. regards, Jason
  6. Hi, I'm looking for instructions for building the out of box SD card image for the Genesys ZU xczu3EG from the source repositories. I have been unable to find complete build instructions using a google search or in the repositories them selves. regards, Jason
  7. Hi, I have have two Genesys ZU boards. Powered up out of the box the ERR LED comes on and there is no activity on the terminal. The quick start guide says I just connect the usb, power them up, and Linux should boot on the terminal. When I connect the USB I see the two new COM ports in Tera Term, but when the board powers on the ERR LED comes on right away and there is no activity on the terminal. The preloaded SD card is in the slot and the jumper is set to SD. How do I resolve this issue? regards, Jason
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