hi, i simulate a sinewave at 1khz on system generator , the clocking tab is : FPGA clock 20khz and simulink sys period 1/20000 , simulation is ok but when a genrate on hardware (nexys4) the sine wve is 0.2us on osilloscope (it is the case when FPGA work at 100MHZ default clock)
constraint clock is like this :
create_clock -period 50000.000 -name clk [get_ports clk]
set_property BITSTREAM.General.UnconstrainedPins {Allow} [current_design]
set_property PACKAGE_PIN E3 [get_ports clk]
set_property IOSTANDARD E3 [get_ports clk]
what i must do to ansure the FPGA harware take a 20khz clock in consideration???