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  1. Hi, I found the solution to my Problem. First of all a short update of my problem: My application completely fits into the BRAM, so I dont want to use the Microblaze to Load Program Memory to DDR. I just want to use the QSPI to store my hardware+application to be able to boot from it. (Therefore I dont need to focus on the SREC application template) The solution: 1. I need to generate a .mcs file out of the download.bit in SDK folder. As far as I understood, this download.bit is merged from the hardware.bit file and the application .elf file. The only way I found to genereate th
  2. Hi, I had no Problem to program the qspi from Vivado by following the guide from the resource center. But that only gives me the hardware configuration. I also need to Program the Microblaze from the SDK. In previous projects with the ISE tool I used the iMPACT tool from Xilinx, but that doesn't seem to be available!? What is the best and easiest way to do a full programming (hardware and microblaze software) from the SDK? I am using the Vivado 2015.3 WebPACK with a Nexys4-DDR Board. Thanks party-pansen
  3. Hi Tommy, thanks for that information. I'll try this workaround with 200MHz input clock. Do I need to "hack" the mig controller to get this 100MHz output pin "ui_addn_clk_0" or will it be created automatically? Regards party-pansen
  4. Hi, a few days ago I started with Vivado 2015.3 and the digilent Board Files provided on this web site. I followed the example instructions for Microblaze setup, but I always get a pulse width error of -0.736ns as shown in the attached screenshot: Is this a known Problem? Can anyone judge if it is critical and if yes how to solve it? At some first tests accessing the memory everything seems to work fine... Best regards party-pansen