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  1. Dear All, for a class experiment, I am interesting to modify the Eclypse Z7 Low Level Zmod ADC DAC Demo In order to disconnect the FIR FILTER and make the students insert some custom VHDL modules the top module of the FIR filter has the following ports entity Filter_Top_Level is Port ( SysClk : in STD_LOGIC; sysRst_n : in STD_LOGIC; sysInitAdcDone : in STD_LOGIC; sysInitDacDone : in STD_LOGIC; sysAdcCh1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); sysDacCh1 : OUT STD_LOGIC_VECTOR(13 DOWNTO 0); sysDacCh2 :