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  1. Like
    Bianca got a reaction from Cristian.Fatu in DMM Shield   
    Hi @Zoran,
    Those transistors have the collector shorted to the base and they function as a diode. The circuit there is basically a clamping circuit to limit the over and under voltage.
  2. Like
    Bianca got a reaction from Takashi "The Yaka mein" in Technical question for Nexys4-DDR (410-292)   
    Hi Takashi,
    I am not very sure what you are asking. If you are referring to the XADC Pmod, I can tell you that this is wired to the auxiliary analog input pins of the FPGA. The pins can be configured as analog input, or digital input/output. The XADC is a dual channel 12-bit ADC converter and can go up to 1MSPS.
    The VCC pin of the Pmod is able to provide 3.3V . The FPGA Bank (Bank 15) where the analog pins are connected is also powered at 3.3V.
    If you want more information about the XADC and how you can use it, you can check the Xilinx UG480
    For other information you can also check the Reference Manual:
  3. Like
    Bianca got a reaction from Cristian.Fatu in what Zynq-7020 board would you recommend, Zybo , ARTY Z7, PYNQ-Z1?   
    Well, the FPGA is the same, so what you want to look at, are the other features like the memory, Audio, Digital I/O. Maybe you also want to use some buttons or switches at some point, and you want them on the board and not as expansion. 
    Between PYNQ Z1 and Arty Z7, the only difference is that the PYNQ has a microphone and Arty Z7 doesn't, otherwise they are identical from the specs point of view.
    With this in mind, I will talk about the comparison between the Arty Z7 and Zybo Z7...
    They both have HDMI In and Out, but if you also want Audio codec you can find that only on Zybo Z7. the DDR3 is 1024MB on ZyboZ7 and 512MB on Arty Z7. 
    If you are interested in more DIO pins, Arty Z7 has 9 more through the Arduino expansion shield. 
    Zybo Z7 though, comes with the Pcam connector in case at some point you want to switch the type of camera used. 
    You can find below a table with the specs from our last year catalog. I hope this gives you a better overview to what might help you better in your work. You'll probably get your work done with either one. My personal suggestion, if you allow it, is to go with the Zybo Z7 as it was designed to be used for video processing, as we added the camera. The double memory is also a big advantage. Arty Z7 and PYNQ Z1 are more into the entry and hobby level. Choose what has the optimal set of features to ease your work and what fits your budget best. 

    Best regards,
  4. Like
    Bianca got a reaction from Shalom in BNC Adapter: 0 ohm vs 50 ohm Waveform Generator   
    Hi @Shalom,
     In case you want to match the output you'll use the 50Ohm jumper position in order to have adaptation. In this case your amplitude will be divided by 2. In the case you want to use the Gavegen just as a voltage source and don't want to reduce the amplitude,  you can leave it to 0V. 
  5. Like
    Bianca reacted to Ciprian in out-of-the-box Petalinux   
    Hi @wpless
    If you just want to run it and make no changes to it you can use Digilents releases for it. Here:  v0.2 is the latest and it will contain and .img file which you can flash to your SDcard and have everything set up for you.
    Digilent, as far as I know, doesn't provide SDcards with the Eclypse-Z7 "box" but you can have a fully functional debian running on the board, without rebuild, with the above link.
  6. Like
    Bianca got a reaction from JColvin in HS-3 support for Vivado 2019.2 and Versal   
    Hi @sktam
    We contacted Xilinx to ask about the Vivado support with the Digilent cables and they said that the latest public hw_server (2019.2) supports Digilent cables programming Versal devices. Therefore if you have a Digilent cable you can continue using it for vck190  eval board and on your “chip-down” Versal design.
    Best regards,
  7. Like
    Bianca got a reaction from Wyllyam in BASYS3 SPI x4 PROGRAMMING ERROR 27-3161   
    Hello @RBS,
    The problem with the spaces on the path is well known for Vivado. Also the SDK won't work if the path is too long. If you store your project in a work directory that has more than one or two sub folders, won't work. The best and safest way is to work on desktop. You are not the only one who encountered this problem so don't worry.
    Best regards,
  8. Like
    Bianca got a reaction from JColvin in Looking for Diode D3 part number in Nexys A7   
    Hi @Jayshree,
    Here you have the datasheet of the Diode.
  9. Like
    Bianca got a reaction from mladenik in Pmod DA4 Stopped Working   
    Hi @mladenik,
    I'm sorry your PMOD failed, It's a very long shot to get it work again since it's only one chip and doesn't have extra things. Most likely something wend wrong it it, either from an ESD event or some kind of short circuit. 
    If you can, you can at least exclude a short circuit by measuring the impedance between VCC /DATA pins and GND. If you don't have power at all, if you don't have the 3V3, it can be either that it's a short circuit on one of the capacitors or that something went wrong with the chip. If it's a capacitor,  you take it down,  and it might have a small chance to work again. Normally a burned capacitor can be visible optically. 
    If the filtering capacitors are fine, then you should think give up on the PMOD if you are not willing to replace the DAC. 
    Best regards,
  10. Like
    Bianca got a reaction from JColvin in Evaluation boards   
    Hi @mariushvn,
    There is no difference between them. The original was Artix-7 35T Arty FPGA Evaluation Kit and then we re-branded the Arty category by sticking to the same form factor but with different FPGAs (artix, spartan, zynq). To make sure there won't be confusion between the products, the original Arty is called now Arty A7. The new thing is that it can be found now also with a bigger FPGA, the 100T not only with the 35T how it was the original. 
    Best regards,
  11. Like
    Bianca reacted to BogdanVanca in Setting the Pcam 5C's internal registers   
    Hello @bitslip,
    Things are a little bit more complicated.  Indeed, for changing the resolution you have to rewrite some registers. But you also need to make sure that the Video Trimming controller ip generates the required constants for you resolution. I wouldn't recommend to write all the needed registers from the control interface (it would be agonising) Instead I would go with the existent logic for changing the resolution, which is adding a new structure with all the register values. As an example, you can check the OV5640.H file. I much simple and quicker solution would be to use our video scaller ip. This ip was written in HLS and it was used in the  fmc pcam adapter demo for re-scalling the video at a 640x480 resolution.  You can check the design in here:
    Best Regards,
    Bogdan Vanca 
  12. Like
    Bianca got a reaction from JColvin in How to restore FT2232 EEPROM back to factory settings?   
    Hi @svet-am,
    This solution works just for the Digilent boards. Please contact Xilinx for support in order to fix your KCU1500 board.
    Best regards,
  13. Like
    Bianca got a reaction from [email protected] in Internet (no wifi available) connection to Arty A7 board   
    Hi @josejose,
    There is a Digilent Design Contest project, the winners from this year. They made a project that controlled a Zybo Z7 over Internet. It was a platform for students to prototipe and test their HDL design. The project it's a bit more complex; they segmented the memory and allowed multiple users to access different peripherals of the board at the same time. It's very well documented so you might find some things to help you there. The project works and you can contact them over github if something is unclear. Here is the git repo  and here is the documentation.
    Maybe it can help you. 
  14. Like
    Bianca got a reaction from Cristian.Fatu in *.xdc file upload (Zynq 7000 EPP, 7Z020 CLG 484-1, Revision D)   
    Hi @Zed_Guy,
    The ZedBoard XDC file is available on out GitHub here:
    I looked in your document and I saw that they changed the name of the ports in the XDC to match with their projects. You can either use in the project, the names used in the XDC or change in the XDC the names according to your project. By the fact that they are using "my_constraints.xdc" implies that they created a XDC file specific for the project in the guide, and probably used just what they needed. 
    Normally, where you found the project and the guide, you should've been able to find the that XDC because it is not a generic Rev D XDC.
    The pins marked in the document with red, are linked to the first 4 pins in the JA pmod connector. You can find them in the official XDC. 

    You have two choices. Contact Avnet  and ask for that project specific XDC, or take the XDC from us and change it according to your project. 
    Best regards,
  15. Like
    Bianca got a reaction from Cristian.Fatu in Uploading a bitstream and running an application from Flash memory   
    Hi @NotMyCupOfTea,
    We have an old ZedBoard programming tutorial. This was not checked for a while so might contain errors. Also, it's made for older versions of Vivado SDK. Things might be a bit different with the current versions. It goes through the steps @xc6lx45 mentioned above. I hope it helps.[]=qspi 
  16. Like
    Bianca got a reaction from tjw in Pmod OLEDrgb thickness?   
    Hi @BradLevy,
    We don't have a 3D drawind for the Pmod OLEDrgb but i measured it and it was 4.45 mm (~0.175") in thickness. And from the attached picture you can see that it's not higher than the Pmod Connetor. 

    I hope this helps.
  17. Like
    Bianca got a reaction from Cristian.Fatu in Unable to download Adept 2   
    Hi @Mahmood ul Hassan,
    I just tried and it works. You have to fill in the form and the download will start.
  18. Like
    Bianca reacted to Cristian.Fatu in tera term for two pmods   
    The PmodAD2 communicates over I2C protocol with the main board on which the Pmod is plugged. The PmodAD2 has no UART / USB capabilities.
    It is the main board that communicates - using its USB-UART capability - with the PC. Connecting the board using a USB cable creates a COM port on the PC. When you open a TeraTerm (or other terminal) connection, you select the COM port.
    Therefore a possible approach could be to have 2 PmodAD2 connected to a single main board, in different Pmod connectors. The SDK application should gather the AD2 data (measurements), format a text message containing these measurements, and then sending the text message over UART to the PC, to be later visualized in a terminal.
    What application are you running on the FPGA board ? You should modify it to read the other Pmod as well.
  19. Like
    Bianca got a reaction from Chouchene in JTAG-HS2 firmware erased by accident   
    Hi @Chouchene,
    You have a private message.
  20. Like
    Bianca got a reaction from freakuency in Arduino/chipKIT Shield Connector Measurements   
    Hi @freakuency,
    On Arty Z7 reference page you can see a step model for the board on Additional Resources section:
    If the step file doesn't help you, You have here some dimensions for the Arty Z7. 
  21. Like
    Bianca got a reaction from AAle in Pmod IA Impedance Analyzer C Code   
    Hi Alejandro,
    Unfortunately, we don't have C code available for PmodIA, however, Analog Devices who manufactures the AD5933, that's the core of the PmodIA has some reference projects. They have an example with the zedboard and the files might help you. You can check on their github, here: 
    You can also take a look on their wiki page, here: 
  22. Like
    Bianca got a reaction from vahid in I want to blink LED   
    Hello hilarikas,
    I just checked again your files and saw some things that I missed last time I looked. I saw that you tried to assign your clock signal and one led. Unfortunately you confused the XDC file with the UCF file.
    Both UCF and XDC are contraints files. UCF is used with ISE and XDC is used with Vivado. The main difference between them is the syntax. What you tried to do was writing in the XDC the with the syntax from UCF. It won't work. 
    XDC syntax for the clock:
    ## Clock Signal
    #set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
    #set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
    UCF syntax for the clock:
    ## Clock signal
    #NET "clk"   LOC = "E3"    | IOSTANDARD = "LVCMOS33"; (taken from Nexys4 UCF)
    What you tried to do:
    ##NET "refclk" LOC = "AD11";
    Then, you cannot use the Genesys2 clock like this. It's a differential clock and you'll have to use a primitive to instantiate it. As you can see you have a sysclk_n and a sysclk_p. You'll have to use IBUFG primitive. you can find more information in Xilinx documentation. This primitive will allow you to use the clock. The primitive looks like this:
       generic map (
          DIFF_TERM => FALSE, -- Differential Termination 
          IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
          IOSTANDARD => "DEFAULT")
       port map (
          O => O,  -- Buffer output
          I => I,  -- Diff_p buffer input (connect directly to top-level port)
          IB => IB -- Diff_n buffer input (connect directly to top-level port)
    Where, O is a clock signal you will declare as standard_logic. (Not Port, but Signal) in your case you wanted refclk and I and IB are the two parts of the differential clock. it would look like this:
       generic map (
          DIFF_TERM => FALSE, -- Differential Termination 
          IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
          IOSTANDARD => "DEFAULT")
       port map (
          O => refclk,  -- Buffer output
          I => sysclk_p,  -- Diff_p buffer input (connect directly to top-level port)
          IB => sysclk_n -- Diff_n buffer input (connect directly to top-level port)
    After this when your code and your XDC are ready synthesize your project. Don't generate bitstream just synthesize then open the synthesized design. You'll have to assign that clock to the design, in order to know that is a clock signal.  Attached to this post is a word document with a tutorial on how to assign the clock.
    At the end of this reload your XDC file. You'll have an option on the top where you have the page open and if all works well you'll see that it will add an extra line on the bottom of your XDC. Mine looks like this:
    create_clock -period 5.000 -name sysclk_p -waveform {0.000 2.500} [get_ports sysclk_p]
    After you finished, generate your bitstream and put it on the board. Attached here you'll also find an example of a working code that counts on the leds and the correct uncommented XDC file. 
    Best regads,
    Asign Clock.docx
  23. Like
    Bianca got a reaction from Djsnzheusj in ARTY A7-35 REV E.   
    Hi @Djsnzheusj,
    The XDC for D.0 will work. We made a spin for the power supplies. Nothing in the FPGA configuration was affected by the new PCB spin.
  24. Like
    Bianca got a reaction from aeon20 in Hello world like example for Digilent Nexys A7?   
    Hello @aeon20,
    Welcome to the forum and to the world of FPGA. 
    There are some tutorials available. I will guide you to this one on Vivado that actually does led blinking:
    You can find some resources here: and if you look for Nexys 4DDR (which is the old name for Nexys A7) you can find other things. 
    I suggest you to start with led blinking. Connecting the switches to the leds, trying to work with the seven segment display, and moving forward to the VGA.
    We have some components example in the learn section of our website: 
    I think this might be a good start for you until you get your hear around the board.
    I hope you'll enjoy the learning process.
    Best regards,
  25. Like
    Bianca got a reaction from elizegi in How to restore FT2232 EEPROM back to factory settings?   
    Hi @elizegi,
    You'll have a private message in a few minutes...