Bianca

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  1. Like
    Bianca got a reaction from JColvin in Evaluation boards   
    Hi @mariushvn,
    There is no difference between them. The original was Artix-7 35T Arty FPGA Evaluation Kit and then we re-branded the Arty category by sticking to the same form factor but with different FPGAs (artix, spartan, zynq). To make sure there won't be confusion between the products, the original Arty is called now Arty A7. The new thing is that it can be found now also with a bigger FPGA, the 100T not only with the 35T how it was the original. 
     
    Best regards,
    Bianca
  2. Like
    Bianca reacted to BogdanVanca in Setting the Pcam 5C's internal registers   
    Hello @bitslip,
    Things are a little bit more complicated.  Indeed, for changing the resolution you have to rewrite some registers. But you also need to make sure that the Video Trimming controller ip generates the required constants for you resolution. I wouldn't recommend to write all the needed registers from the control interface (it would be agonising) Instead I would go with the existent logic for changing the resolution, which is adding a new structure with all the register values. As an example, you can check the OV5640.H file. I much simple and quicker solution would be to use our video scaller ip. This ip was written in HLS and it was used in the  fmc pcam adapter demo for re-scalling the video at a 640x480 resolution.  You can check the design in here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-fmc-pcam-adapter-demo/start
     
    Best Regards,
    Bogdan Vanca 
     
  3. Like
    Bianca got a reaction from JColvin in How to restore FT2232 EEPROM back to factory settings?   
    Hi @svet-am,
    This solution works just for the Digilent boards. Please contact Xilinx for support in order to fix your KCU1500 board.
    Best regards,
    Bianca
  4. Like
    Bianca got a reaction from D@n in Internet (no wifi available) connection to Arty A7 board   
    Hi @josejose,
    There is a Digilent Design Contest project, the winners from this year. They made a project that controlled a Zybo Z7 over Internet. It was a platform for students to prototipe and test their HDL design. The project it's a bit more complex; they segmented the memory and allowed multiple users to access different peripherals of the board at the same time. It's very well documented so you might find some things to help you there. The project works and you can contact them over github if something is unclear. Here is the git repo  and here is the documentation.
    Maybe it can help you. 
    Bianca
  5. Like
    Bianca got a reaction from Cristian.Fatu in *.xdc file upload (Zynq 7000 EPP, 7Z020 CLG 484-1, Revision D)   
    Hi @Zed_Guy,
    The ZedBoard XDC file is available on out GitHub here: https://github.com/Digilent/digilent-xdc/
    I looked in your document and I saw that they changed the name of the ports in the XDC to match with their projects. You can either use in the project, the names used in the XDC or change in the XDC the names according to your project. By the fact that they are using "my_constraints.xdc" implies that they created a XDC file specific for the project in the guide, and probably used just what they needed. 
    Normally, where you found the project and the guide, you should've been able to find the that XDC because it is not a generic Rev D XDC.
    The pins marked in the document with red, are linked to the first 4 pins in the JA pmod connector. You can find them in the official XDC. 

     
    You have two choices. Contact Avnet  and ask for that project specific XDC, or take the XDC from us and change it according to your project. 
     
    Best regards,
    Bianca
  6. Like
    Bianca got a reaction from Cristian.Fatu in Uploading a bitstream and running an application from Flash memory   
    Hi @NotMyCupOfTea,
    We have an old ZedBoard programming tutorial. This was not checked for a while so might contain errors. Also, it's made for older versions of Vivado SDK. Things might be a bit different with the current versions. It goes through the steps @xc6lx45 mentioned above. I hope it helps.
    https://reference.digilentinc.com/learn/programmable-logic/tutorials/zedboard-programming-guide/start?s[]=qspi 
    Bianca 
  7. Like
    Bianca got a reaction from tjw in Pmod OLEDrgb thickness?   
    Hi @BradLevy,
    We don't have a 3D drawind for the Pmod OLEDrgb but i measured it and it was 4.45 mm (~0.175") in thickness. And from the attached picture you can see that it's not higher than the Pmod Connetor. 

     
    I hope this helps.
     
    Regards,
    Bianca
  8. Like
    Bianca got a reaction from Cristian.Fatu in Unable to download Adept 2   
    Hi @Mahmood ul Hassan,
     
    I just tried and it works. You have to fill in the form and the download will start.
     
    Regards,
    Bianca
  9. Like
    Bianca reacted to Cristian.Fatu in tera term for two pmods   
    Hello,
    The PmodAD2 communicates over I2C protocol with the main board on which the Pmod is plugged. The PmodAD2 has no UART / USB capabilities.
    It is the main board that communicates - using its USB-UART capability - with the PC. Connecting the board using a USB cable creates a COM port on the PC. When you open a TeraTerm (or other terminal) connection, you select the COM port.
    Therefore a possible approach could be to have 2 PmodAD2 connected to a single main board, in different Pmod connectors. The SDK application should gather the AD2 data (measurements), format a text message containing these measurements, and then sending the text message over UART to the PC, to be later visualized in a terminal.
    What application are you running on the FPGA board ? You should modify it to read the other Pmod as well.
     
  10. Like
    Bianca got a reaction from Chouchene in JTAG-HS2 firmware erased by accident   
    Hi @Chouchene,
    You have a private message.
    Regards,
    Bianca
  11. Like
    Bianca got a reaction from freakuency in Arduino/chipKIT Shield Connector Measurements   
    Hi @freakuency,
     
    On Arty Z7 reference page you can see a step model for the board on Additional Resources section: https://reference.digilentinc.com/reference/programmable-logic/arty-z7/start
    If the step file doesn't help you, You have here some dimensions for the Arty Z7. 
    Regards,
    Bianca
    Arty_Z7_Drawing.pdf
  12. Like
    Bianca got a reaction from AAle in Pmod IA Impedance Analyzer C Code   
    Hi Alejandro,
    Unfortunately, we don't have C code available for PmodIA, however, Analog Devices who manufactures the AD5933, that's the core of the PmodIA has some reference projects. They have an example with the zedboard and the files might help you. You can check on their github, here: https://github.com/analogdevicesinc/no-OS/tree/master/Pmods/PmodIA 
    You can also take a look on their wiki page, here: https://wiki.analog.com/resources/fpga/xilinx/pmod/ad5933 
     
    Regards,
    Bianca
  13. Like
    Bianca got a reaction from vahid in I want to blink LED   
    Hello hilarikas,
     
    I just checked again your files and saw some things that I missed last time I looked. I saw that you tried to assign your clock signal and one led. Unfortunately you confused the XDC file with the UCF file.
    Both UCF and XDC are contraints files. UCF is used with ISE and XDC is used with Vivado. The main difference between them is the syntax. What you tried to do was writing in the XDC the with the syntax from UCF. It won't work. 
    XDC syntax for the clock:
    ## Clock Signal
    #set_property -dict { PACKAGE_PIN AD11  IOSTANDARD LVDS     } [get_ports { sysclk_n }]; #IO_L12N_T1_MRCC_33 Sch=sysclk_n
    #set_property -dict { PACKAGE_PIN AD12  IOSTANDARD LVDS     } [get_ports { sysclk_p }]; #IO_L12P_T1_MRCC_33 Sch=sysclk_p
     
    UCF syntax for the clock:
    ## Clock signal
    #NET "clk"   LOC = "E3"    | IOSTANDARD = "LVCMOS33"; (taken from Nexys4 UCF)
    What you tried to do:
    ##NET "refclk" LOC = "AD11";
     
    Then, you cannot use the Genesys2 clock like this. It's a differential clock and you'll have to use a primitive to instantiate it. As you can see you have a sysclk_n and a sysclk_p. You'll have to use IBUFG primitive. you can find more information in Xilinx documentation. This primitive will allow you to use the clock. The primitive looks like this:
    IBUFDS_inst : IBUFGDS
       generic map (
          DIFF_TERM => FALSE, -- Differential Termination 
          IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
          IOSTANDARD => "DEFAULT")
       port map (
          O => O,  -- Buffer output
          I => I,  -- Diff_p buffer input (connect directly to top-level port)
          IB => IB -- Diff_n buffer input (connect directly to top-level port)
       );
    Where, O is a clock signal you will declare as standard_logic. (Not Port, but Signal) in your case you wanted refclk and I and IB are the two parts of the differential clock. it would look like this:
    IBUFDS_inst : IBUFGDS
       generic map (
          DIFF_TERM => FALSE, -- Differential Termination 
          IBUF_LOW_PWR => TRUE, -- Low power (TRUE) vs. performance (FALSE) setting for referenced I/O standards
          IOSTANDARD => "DEFAULT")
       port map (
          O => refclk,  -- Buffer output
          I => sysclk_p,  -- Diff_p buffer input (connect directly to top-level port)
          IB => sysclk_n -- Diff_n buffer input (connect directly to top-level port)
       );
    After this when your code and your XDC are ready synthesize your project. Don't generate bitstream just synthesize then open the synthesized design. You'll have to assign that clock to the design, in order to know that is a clock signal.  Attached to this post is a word document with a tutorial on how to assign the clock.
    At the end of this reload your XDC file. You'll have an option on the top where you have the page open and if all works well you'll see that it will add an extra line on the bottom of your XDC. Mine looks like this:
    create_clock -period 5.000 -name sysclk_p -waveform {0.000 2.500} [get_ports sysclk_p]
    After you finished, generate your bitstream and put it on the board. Attached here you'll also find an example of a working code that counts on the leds and the correct uncommented XDC file. 
    Best regads,
    Bianca
    Asign Clock.docx
    LED.vhd
    Genesys2_H.xdc
  14. Like
    Bianca got a reaction from Djsnzheusj in ARTY A7-35 REV E.   
    Hi @Djsnzheusj,
    The XDC for D.0 will work. We made a spin for the power supplies. Nothing in the FPGA configuration was affected by the new PCB spin.
    Regards,
    Bianca
  15. Like
    Bianca got a reaction from aeon20 in Hello world like example for Digilent Nexys A7?   
    Hello @aeon20,
    Welcome to the forum and to the world of FPGA. 
    There are some tutorials available. I will guide you to this one on Vivado that actually does led blinking: https://reference.digilentinc.com/vivado/getting_started/2018.2
    You can find some resources here: https://reference.digilentinc.com/learn/programmable-logic/tutorials/start and if you look for Nexys 4DDR (which is the old name for Nexys A7) you can find other things. 
    I suggest you to start with led blinking. Connecting the switches to the leds, trying to work with the seven segment display, and moving forward to the VGA.
    We have some components example in the learn section of our website: https://learn.digilentinc.com/classroom/ 
    I think this might be a good start for you until you get your hear around the board.
    I hope you'll enjoy the learning process.
    Best regards,
    Bianca
  16. Like
    Bianca got a reaction from elizegi in How to restore FT2232 EEPROM back to factory settings?   
    Hi @elizegi,
    You'll have a private message in a few minutes...
    Regards,
    Bianca
  17. Like
    Bianca got a reaction from JColvin in ARTY S7 PMICs   
    Hi @fpgadev,
    The redesign wasn’t due to any flaws with the initial line. We switched to the DA9062 to better align the Arty S7 with the products promoted by our partners. 
    As for the DA9062 configuration, what I can tell you is that we are using a custom configuration that gets programmed into the device's non-volatile memory using a Dialog DA9061/2/3 In-Circuit Programmer (232-18-A Programmer Board) as part of the Arty S7 manufacturing test. If you want to design the DA9062 into a product then I strongly suggest ordering the DA9062-EVAL1 and testing out different configurations on the eval board.
    Best regards,
    Bianca
  18. Like
    Bianca reacted to BogdanVanca in How to launch Digilent hdmi FMC with zc702 board   
    Hello @Blake,
    I've created for you an image that test your FMC-HDMI adapter. It does a basic data transfer between the HDMI output of the ZedBoard and both of the adapter hdmi inputs. Prior to this it also uses all the I2C lines. Please check the .rar attached file. In order to recreate the test, please fallow the fallowing steps:
    1.Make sure that you have everything in place, check the bellow instructions and the first image.
    Connect USB cable from PC to ZED USB PROG port (J17) Connect USB cable from PC to ZED UART port (J14) Connect FMC-HDMI board to FMC connector J1 (of ZED) Connect Power cable to J20 (of ZED) Set mode jumpers for JTAG programming (all to GND) Set J18 (of ZED) jumpers to 3V3 or 2V5. I'v tested both variants. Create a loop between HDMI-OUT J9(ZED) and FMC-HDMI IN1 of the adapter. Turn ZED board on 2. Open Vivado (I used Vivado 2017.4).
    Open Vivado, and click on Open Hardware Manager within the Welcome Page. After this click on Auto-Connect. You should see the Zed into the upper left panel.Check the image bellow.
    3. Add Configuration Memory Device
    Right click on xc7z020_1 and choose "Add Configuration Memory Device". Check image bellow. 4. Choose the right memory device for ZED. 
    Please choose "s25fl256s-3.3v-qspi-x1-dual_stacked" from the list. Click to program the device. Check images bellow.  
     5.Program the device with the files attached to this message.
    For "Configuration file" you choose BOOT.bin. For "Zynq Fsbl" you choose fsbl.elf.  Click OK.
    6. Wait until it gets programmed. After finish, you click OK. 
    7. Prepare the board for testing. 
    Open a serial terminal, termite, putty, teraterm etc. Find the COM port and choose 115200 for baud rate. Set jumpers for QSPI programming (MIO5 on 3V3 and SIG, the others on 3V3 and GND). Power OFF the Board. Power ON  the Board.  The image should boot. See the image bellow.  
    8.Do the actually test.
    Make sure that the HDMI-OUT (ZED) is connected to HDMI-IN1 of the FMC-HDMI adapter.  Press ENTER. Wait for the test to finalize. 
    Make sure that the HDMI-OUT (ZED) is connected to HDMI-IN2 of the FMC-HDMI adapter. Make sure that your adapter is not loose.  Press ENTER. Wait for the test to finalize. 9.Check the results, and give me an update  .
     
    image.rar
  19. Like
    Bianca got a reaction from JColvin in Differences in Max32 and chipKIT Max32   
    @raouf,
    Like James said, they are the same products, just re-branded. If they have Chipkit Max32 Rev E, It's the same with the Max32. All the products from the Chipkit line were re-branded but they are the same. 
    As a distributor they can make an order to Digilent for a specific product if they don't have it, but like I said, just the box and the inscription on the board are different.
    I hope this helps.
    Best regards,
    Bianca
  20. Like
    Bianca reacted to attila in AD2 over voltage :-(   
    Hi @peter taylor
    This was a ferrite between the Analog Discovery and USB ground. Supposed to filter noise from USB cable/PC which acted as a fuse...
    You can solder a simple short instead this ferrite. Hopefully only this was damaged.
    Be careful. The devices and circuits should have the same ground. The AD ground is connected to the PC ground over the USB cable.
     
  21. Like
    Bianca reacted to Notarobot in Zebo board: one connector missing   
    The JF connector is physically connected to MIO ports. These ports allows to connect such peripheral as UART and CAN to PS. Configuration of such connections is done in the processing_system7_0 block in Vivado.
    In my understanding they are not present in the block design because there is no easy way to utilize it with PL.
    It is always helpful to check the schematic diagram of the board.
    Hope I've answered your question.
  22. Like
    Bianca reacted to elodg in Nexys Video "Feet"   
    https://www.fastenal.com/products/details/0146057
    https://www.fastenal.com/products/details/28783
  23. Like
    Bianca got a reaction from JColvin in Reference Schematic for the Pmod USBUART2   
    Hi @MaelXD,
    Can you please show me a picture with the USBUART2?
    We were not aware of a second revision of USBUART, neither I could track it on the store and engineering database. Did you purchase it from our store? and when?
    Thanks,
    Bianca
  24. Like
    Bianca got a reaction from JColvin in HS1 JTAG Circuit   
    Hello @anshumantech,
    The schematic is unavailable on purpose. It contains 3rd party designs and we can't release it.
    Best regards,
    Bianca
  25. Like
    Bianca got a reaction from Mayur in Arty A7-35T Xilinx WebPack (free version) compatibility   
    Hello @Mayur,
    ISE is no longer supported by Xilinx. When the latest version of ISE, 14.7 was released they already had the XC7A100T and XC7A200T. The newer versions of Artix 7 FPGA, like the 35T for example, were released after ISE 14.7, and therefore are not supported. 
    35T variant will work only with Vivado. You can use the Webpack licence (free version) of Vivado with the Arty.
    Best regards,
    Bianca