Bianca

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Everything posted by Bianca

  1. Hello Toby, Unfortunate, we cannot provide the full layout of the board and we do not have hyperlynx models of the lines. What I can tell you is that it respects the FMC standard 50Ohm impedance for single ended and 100ohm impedance for differential traces. Also I can give you the traces length for the FMC connector so you can calculate the speed. Attached here you can find the traces length. I hope this helps! Best regards, Bianca FMC_traces.txt
  2. Nice project! Thank you for sharing it with us! JColvin, about windows10, even if it's not yet official from Xilinx, Vivado 2015.4 does work on W10. I tested it on some projects with Basys3 and it worked flawless. You don't need extra configuration for it, just the classical installation.
  3. Hello, If you are asking for the solution from the exercise on Real Analog, you can find the solutions here . If you are looking for homework solution, we don't have them. On that page you can find the whole documentation. I hope it helps. Best regards, Bianca
  4. Hello, We don't have any plans to change the ZedBoard with a new board but we're always working on something new and exciting. You can never know
  5. Hello Tifei, It is right, if you remove R408 you can power VDAJ with external power source. Once you've removed the resistance, IC37 will be left open, won't power anything and IC34 won't measure the current anymore. You have to take care of the circuits that are powered from VADJ, to be compatible with the voltage value you want to bring from your external source. Also you have to respect the power-up/power-down sequence with the other internal power sources. For example, it's not recommended to turn off the board with VADJ externally powered. Best regards, Bianca
  6. Bianca

    Zybo base system design

    Hello, Well first of all, the processor has the data bus HP0 and it uses it to read/write from DDR. VDMA is used to automatically display on the monitor, so the VDMA is connected to HP0 bus in order to r/w in DDR and the user needs to control the VDMA to access the memory. The AXI interface is used for the communication between the processor and the FPGA. You need it to control from the processor the modules utilized in the FPGA. Regarding the clocking, the 100MHz clock is created as standard for the ip cores we create to use in the project. In general the cores works on 100MHz. The
  7. Bianca

    DDR3 GENESYS2

    Hello, To generate a MIG without AXI interface you can use this document from Xilinx: http://www.xilinx.com/support/documentation/ip_documentation/mig_7series/v2_1/ug586_7Series_MIS.pdf Also there you will find a tutorial to debug your code and check your signals. This can help you fix your problem. Best regards, Bianca
  8. Hello, You should try to use Vivado 2015.2. This is the version used to make the base system design for Arty. I tried last week to build the program using Vivado 2015.3 with no success but I could do it with Vivado 2015.2
  9. Hello Nick, I want to know the Operating System are you using. I downloaded the project from https://reference.digilentinc.com/arty:basedesign What is important to this project is that it was created on board not on the fpga details so you need to introduce the board files into Vivavo here is a tutorial on how can you make that and how to get that files. https://reference.digilentinc.com/vivado:boardfiles2015 After I put my board files into Vivado's installation folder I generated again the project and worked just fine. Best regards, Bianca
  10. Hello, In the learn section of our website you can find various tutorials and documents that can help you learn more. You'll find there tutorials for ISE and VIVADO, some projects and other stuff. On the xilinx website you could also find some documentation. Here is a link to our "Learn" section: https://learn.digilentinc.com/classroom/ Also here in our wiki you can find textbooks: https://reference.digilentinc.com/doku.php#textbooks Best regards, Bianca
  11. Still nothing. At least for the next few months it won't be ready. We are working on it but can't give you a date of release... Best regards, Bianca PS: I saw your adapter. Nice work.
  12. Hello Patrick, We don't have finished the implementation of Microblaze on Arty using FreeRTOS. It is not known when it will be finished. You can keep an eye on Avnet's Arty materials on their site. Best regards, Bianca
  13. Hello, The VMODCAM is not produced anymore but it will be a replacement for it. We don't know yet when it will be ready. We're working on it. Best regards, Bianca
  14. Hello Prabu, We do not have examples on Spartan3 for image processing but I can help you with a VHDL example for Spartan6. The difference between these two is not very significant but Spartan 6 is a more capable FPGA. I don't know if Spartan 3 is capable of image processing. Here you have the Demo project on Atlys that does image processing in order to match the two acquired images and provide an image prepared for 3D colored glasses. https://www.dropbox.com/s/7iij3hkly50h4a8/3D Camera Demo Project.zip I hope this helps you. Regards, Bianca