Forum Managers
  • Content Count

  • Joined

  • Last visited

  • Days Won


Bianca last won the day on February 8

Bianca had the most liked content!

About Bianca

  • Rank
    Prolific Poster

Profile Information

  • Gender
  • Location
  • Interests
    PCB, hardware, electronics, FPGA, power supplies, power electronics

Recent Profile Visitors

4037 profile views
  1. Hi @srss, The DMM Shield is compatible with Mega (as is with Uno, Due). All the pins used by DMM shield are connected to the Arduino Mega. As @kwilber said, there are some extra pins that are not mated with Arduino. We loaded those just to have full compatibility with our Chipkit boards that have the extra rows. As you can see in the picture below. All the signals that the DMM Shield are using are on the outer pins of the connector to assure the compatibility with Arduino. The rest are loaded in case you need to stack other shields on top of the DMM to have access to the chipkit pins. I hope this helps you. Best regards, Bianca
  2. Here you have the board files: and you can follow this tutorial to install them: Copy the contents of the board_files folder Navigate to the board_files folder in the Vivado Installation directory (C:\Xilinx\Vivado\2015.1\data\boards\board_files) - 2015.1 will be replaced with your current version of Vivado Paste the contents into the board_files folder Restart Vivado -Bianca
  3. Hello @aeon20, Welcome to the forum and to the world of FPGA. There are some tutorials available. I will guide you to this one on Vivado that actually does led blinking: You can find some resources here: and if you look for Nexys 4DDR (which is the old name for Nexys A7) you can find other things. I suggest you to start with led blinking. Connecting the switches to the leds, trying to work with the seven segment display, and moving forward to the VGA. We have some components example in the learn section of our website: I think this might be a good start for you until you get your hear around the board. I hope you'll enjoy the learning process. Best regards, Bianca
  4. Hi @Spencer_c, You have a private message. Best regards, Bianca
  5. Hi @elizegi, You'll have a private message in a few minutes... Regards, Bianca
  6. Hi @lukowo, You have a private message. Best regards, Bianca
  7. Hi @chrisdoe, The full schematic of the circuit looks like this. I re-annotated the components : On the right side of the circuit you have the DIO. Normally the voltage in that point is smaller than 5.7V so D1 is closed....Because of that the voltage in the emitter of Q2 is 5.2V On the left side of the circuit the situation is as follows. Q1 is basically a Diode. The voltage in the Base of Q1 is the same with the voltage of Q2. The value of the voltage is 6V- 0.6V that we'll loose across the diode so about 5.4V. Because Q2 has in Emitter 5.2V and in Base a constant 5.4V, Q2 is closed so no current goes through there. Now, if we raise the voltage in the DIO pin above 5.7V, D1 starts to conduct and current starts flowing towards D2. This will increase the voltage level in the emitter. If that goes above the voltage value that Q2 has in base (5.4V), Q2 opens and current starts to flow. This will open Q3 that will pull down. This is the principle behind this circuit. You asked about C223. That one is parallel with Q1 that is basically a diode, so you have a schottky diode. For your second question regarding the protection to 3V3. Because the level voltage is settable. Vrefio was used to detect the middle point and that is done by this circuit The Input divider circuit is redrawn below so you can see it better is as follows: to From this point we can write Milman equation and you have that VFPGA= (510k*Vin+51k*Vrefio)/(510k+51k) and this should be <3.7V which is the max absolute that the FPGA pin can receive. In case something goes wrong, we put en extra protection on the FPGA pin to make sure it won't burn the FPGA bank. I hope this helps you better understand the circuit. Best regards, Bianca
  8. Hi @Striker, You have a private message with the solution. Best regards, Bianca
  9. Hi @fpgadev, The redesign wasn’t due to any flaws with the initial line. We switched to the DA9062 to better align the Arty S7 with the products promoted by our partners. As for the DA9062 configuration, what I can tell you is that we are using a custom configuration that gets programmed into the device's non-volatile memory using a Dialog DA9061/2/3 In-Circuit Programmer (232-18-A Programmer Board) as part of the Arty S7 manufacturing test. If you want to design the DA9062 into a product then I strongly suggest ordering the DA9062-EVAL1 and testing out different configurations on the eval board. Best regards, Bianca
  10. Bianca

    JTAG-SMT3 3D step file

    Hi @mishu, Please see the file attached. Best regards, Bianca JTAG-SMT3.step
  11. Hi @Vlad.K, You have a private message. Best regards, Bianca
  12. Hi @Blake, Sorry for the delay. Your issue was escalated and we'll return with an answer as soon as possible. Thanks for the patience. Best regards, Bianca
  13. Hi @Ian Etheridge You can use whichever SMA antenna that suits your project. However, to do that you will have to solder a Linx Technologies Inc. CONSMA 003.062 module on header J4. Best regards, Bianca
  14. @raouf, Like James said, they are the same products, just re-branded. If they have Chipkit Max32 Rev E, It's the same with the Max32. All the products from the Chipkit line were re-branded but they are the same. As a distributor they can make an order to Digilent for a specific product if they don't have it, but like I said, just the box and the inscription on the board are different. I hope this helps. Best regards, Bianca
  15. Hi @Pavel_47, JF connector is routed to the MIO pins in the PS side of the ZYNQ. This is why you won't find it on the Block Design. You can access it by connecting the pins in the processing system to an interface you desire. Best regards, Bianca