Ghanu Dave

  • Content Count

  • Joined

  • Last visited

About Ghanu Dave

  • Rank

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. This Issue was Resolved thank you to Ana-Maria Balas - Her help was appreciated. Thank you
  2. I have included a PMODESP32 IP in my design. The Design Compiles in Vivado but when I generate SDK related HDF files it give me a message - Any help is appreciated. ====================Message============================================== psys7 General Messages [BD 41-1665] Unable to generate top-level wrapper HDL for the block design '' is locked. Locked reason(s): * Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. List of locked IPs: psys7_PmodESP32_0_0 ================ End of M
  3. Clarification: I have Added PMOD ESP32 to Block Diagram in VIVADO (I do have Zynq UltraScale+ Block on the block digram and also AXI Interconnect block. I want to complete the connections correctly - Thank you so much
  4. I have ZCU102 Xilinx Development Board and I want to Add Digilent PMOD ESP32 to that existing ZYNQ UltraScale Processor section - PSYS7. I have instantiated PMOD ESP32 already on the board - How do I connecto this IP to Zynq UltraScale+ MPSoC - I do have AXI Interconnect Block on My block Design. I can Expand that - so I can connect AXI Interconnect out puts to PMOD ESP32 - DO I NEED UARTLITE? Block in the design or do I just bring the out put directly from PMOD ESP32 - If I do not need UARTlite then how the interface will communicate with outside (Digilent) PMOD ESP32 - I want to make sure my