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Ghanu Dave

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  1. I have integrated or created a block diagram in Vivado 2019.1 version attached - it has Zynq US+ Processor and PMOD ESP32 Module Plus all other required circuit. I am following the examples and try to run main.c https://digilent.com/reference/learn/programmable-logic/tutorials/pmod-ips/start I did not get any success with the end result I expect to get i.e. I am not seeing the following Quotes on my PUTTY terminal (I guess I expect to see it on PUTTY terminal - correct me if I am wrong) xil_printf("Entering Pmod ESP32 Command Line Interface!\r\n"); xil_printf("Enter AT commands to interact with the ESP32\r\n"); It seems my main.c is running (on A53_0 ARM) but it is stuck at Line 63 where is it running and/or waiting for something from user - I guess. Line around 63 are below: while (1) { // TODO: add exit functionality (ctrl-Z?) num_received = ESP32_Recv(&myESP32, &recv_buffer, 1); if (num_received > 0) { xil_printf("%c", recv_buffer); } ANY ADVISE? I am following the Link but there is not much detail on Xilinx SDK - I am not a C Programmer - I am hardware firmware engineer so Please forgive my ignorance. MY GOAL IS TO VALIDATE PMODESP32 Module in my design before I submit the project to Software people. My_Psys7.pdf
  2. I have successfully integrated PMODESP32 in my design (Xilinx ZCU102 - Zynq UltraScale+ MPSoC Board) and now I am validating/testing it using main.c program and related Source from GITHUB. I created wrapper and I am in SDK and able to put appropriate source files under SRC directory. I then tried to compile main.c - BUT ERROR showed up - something like this "xuartps.h" file not found "Multiple markers at this line -Fatal Error: xuartps.h: No such file or directory - Unresolved inclusion:"xuartps.h" Any idea or help on this one is appreciated. THANK YOU SO MUCH
  3. This Issue was Resolved thank you to Ana-Maria Balas - Her help was appreciated. Thank you
  4. I have included a PMODESP32 IP in my design. The Design Compiles in Vivado but when I generate SDK related HDF files it give me a message - Any help is appreciated. ====================Message============================================== psys7 General Messages [BD 41-1665] Unable to generate top-level wrapper HDL for the block design 'psys7.bd' is locked. Locked reason(s): * Block design contains locked IPs. Please run report_ip_status for more details and recommendations on how to fix this issue. List of locked IPs: psys7_PmodESP32_0_0 ================ End of Message =========================
  5. Clarification: I have Added PMOD ESP32 to Block Diagram in VIVADO (I do have Zynq UltraScale+ Block on the block digram and also AXI Interconnect block. I want to complete the connections correctly - Thank you so much
  6. I have ZCU102 Xilinx Development Board and I want to Add Digilent PMOD ESP32 to that existing ZYNQ UltraScale Processor section - PSYS7. I have instantiated PMOD ESP32 already on the board - How do I connecto this IP to Zynq UltraScale+ MPSoC - I do have AXI Interconnect Block on My block Design. I can Expand that - so I can connect AXI Interconnect out puts to PMOD ESP32 - DO I NEED UARTLITE? Block in the design or do I just bring the out put directly from PMOD ESP32 - If I do not need UARTlite then how the interface will communicate with outside (Digilent) PMOD ESP32 - I want to make sure my connection in the PSYS7 Block digram are correct and validate first then I can bring the PMOD pins out side and add required constraint in XDC and other TCL files. Any help appreciated. I am using Vivado 2019.1 version and I do a have correct PMOD IP library loaded and pointed to.
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