Daniel Glasser

Thanks for the response. I have noticed that support for older dev boards is lacking in newer tools. That's not just a problem in the FPGA world; I have some FreeScale reference/development boards that are of an earlier hardware revision, and the Freescale SDK doesn't support them anymore. I also have several SnapDragon development boards that are no longer supported by the manufacturers, and the old support files were removed from their websites. I'm not trying to do anything fancy with the ZedBoard, but it's the only FPGA dev board I have at home.

In Vivado (2021.2) I have created a new project for the ZedBoard that includes: MicroBlaze in microcontroller configuration with 128KiB local memory AXI interrupt controller AXI timer AXI GPIO (x2) MicroBlaze Debug Module UARTlite When I use the design assistant, the uartlite external signals (collectively, "uart_rtl)" are not connected to any IO pins and place design fails. I wrote some constraints to assign 'uart_rtl_rxd" to Pmod connection JA3 and "uart_rtl_txd" to Pmod connection JA4 (FPGA pins Y10 and AA9, respectively): set_property PACKAGE_PIN Y10 [get_ports {uart_rtl_rxd}]; # "JA3" set_property PACKAGE_PIN AA9 [get_ports {uart_rtl_txd}]; # "JA4" Now I get the following during placement ("Implementation/Place Design/Pin Planning/IO Standard"): [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 13. For example, the following two ports in this bank have conflicting VCCOs: uart_rtl_rxd (LVCMOS18, requiring VCCO=1.800) and sys_clock (LVCMOS33, requiring VCCO=3.300) All of the Pmod connections for the PL appear to be in Bank 13, which is 3.3v, so I am looking for a way to tell Vivado that I want "uart_rtl_rxd" and "uart_rtl_txd" to be 3.3V, and while I'm at it, add any necessary pull-ups/pull-downs. I found out about the "Pmod bridge" IP and installed the unpacked "vivado-library-zmod-v1-2091.1-2" into the IP repositories, and have tried to add "pmod bridge 1.1", routed the "tx_0" and "rx_0" from the UART Lite as I saw in one example, but can't figure out how to assign the "Pmod_out_0" I end up with to a specific Pmod connector. The tutorial at https://digilent.com/reference/learn/programmable-logic/tutorials/pmod-ips/2018.2 indicates that the "board" tab should have the Pmod interfaces listed, but they don't appear for the ZedBoard. I have attached the block design that removed the direct connection of the uartlite tx and rx signals to pins and added the Diligent Pmod Bridge IP as "tutorial_1.tcl". I am really out of my depth here. I will continue to seek answers via Google and forum searches, but any suggestions would be appreciated. Thanks. tutorial_1.tcl

Update, of sorts... I have spent the last few months working on the ZCU102 using a design provided by an FPGA engineer. Those particular questions are now answered. I thank all who replied to my earlier questions. I'm now starting to play with the Zedboard at home, and am running into constraint problems (Vivado/Vitis 2021.2) with a simple project, but that's another topic.

Thank you for your interest. I am familiar with FreeRTOS, but not the Xilinx tools. I've used FreeRTOS on Cortex-M3, 4, and 7 in SmartFusion2 FPGAs and STM32 microcontrollers. I have a lighter-weight event driven executive that I wrote that I'd love to see if I can port to MicroBlaze, but FreeRTOS is proven, thus for work I'll stick to that. The thing that the MicroBlaze will be doing is talking to a SPI peripheral over a 40MHz connection for control and receiving messages. To service an event on the device takes at least 3 and more often 5 to 7 transfers of varying length. The eventual target of this is a large-ish Kintex FPGA on an I/O board that is already built. The I/O board connects to a processor board that has a single core PowerPC SoC. For reasons I won't go into here, we cannot use DMA between the main memory and the I/O card, and the RTOS on the PPC is a hard time/space partitioned secure kernel. All I/O access is done from user space, and the schedule gives about 3ms out of every 10 to the partition that relays data between an outboard processor connected via Ethernet and the peripheral (another communications controller). The 3ms of execution time is shared amongst several threads doing different things, not just relaying the data between the two end-points. The current implementation cannot do more than about 20 messages per second due to the latency introduced by periods processing on the APU, so the MicroBlaze will be able to respond to events on the peripheral and put received data into a buffer queue in shared memory, another queue for outbound data from the APU will also be set up. The MicroBlaze will be dedicated to handling the data flow through the peripheral, and all the APU will need to do is to service the queues in shared memory (most of the time). The hope is that we can improve the throughput to about 150 messages/second from the current cap of about 30. The FPGA currently has a specialized SPI master interface that is accessed via the PCIe to AXI bridge, this is being replaced by the MicroBlaze and the shared memory (plus a few other bits). Same Kintex FPGA has 5 GB Ethernet MACs, a heap of UARTs, and a number of other application specific IP blocks. We're going to be using internal BRAM for the MicroBlazes. I really can't go into much more detail, but this should give you the general idea. We're doing this to fix a design decision made years ago without having to redesign an existing I/O board. This is a case of having software fix problems in the hardware design. (I have to run, so this is somewhat unedited.)

Actually, no. I'm looking to set up a MicroBlaze in a Zynq device, whereas the linked document is a "Hello World" for either a MicroBlaze in a device without the Zynq PS or the A9 core in a device with the Zynq PS. It is very clear on that, and the instructions do not work for the ZedBoard if you want to set up a MicroBlaze along side the Zynq PS. Why do I need to do this? I need to get a feel for the MicroBlaze performance, and bring up a FreeRTOS framework with a number of threads, the next step is to (with the help of the FPGA engineers in my department) bring up the A9 and have a shared memory interface between the software running in PetaLinux on the ARM A9 applications processor and the MicroBlaze in the fabric. The MicroBlaze will also interface with some other hardware that is time critical and requires deterministic response times while the applications processor will be doing network communications and running a number of other applications. This is a prototype for a system that won't be on a Zynq board - it's going to be in a Kintex conneted to the applications processor via PCIe. I'm doing this stuff on my own because when the funding comes to do it for real, I will have less than 3 months to bring it all together, and I have never done anything with a MicroBlaze before. At the same time, I hope to learn a bit more about FPGA designs and capabilities. I've worked on several embedded FPGA SoC projects before, but all of those have been Cortex-M microcontrollers. I'm not looking for anyone to solve the shared-memory or other inter-processor communications issues, I just want enough experience with the environment that I can hit the ground running. The ZedBoard was available for me to borrow to take home - I'm looking at this as professional development. I will not be implementing the actual application on this board, but what I learn will help immeasurably when the funding at my work gets turned on. I do thank you for your offer to help, and look forward to anything you can offer. Thanks

Because of the errors I was getting for 2021.1, I uninstalled 2021.1 and installed 2020.1, which is the latest version that I've seen screenshots for, and the Diligent instructions on the page "Getting Started with Vivado IP Integrator and Vitis" write-up asserts that 2020.1 has been tested to have the same screens and behavior as 2019.2. With this, I can now get the board files from GitHub as indicated. Are there any tutorials that walk you through creating a MicroBlaze on a board that does contain a Zynq device (the tutorial I linked abovve is very explicit that the instructions for the MicroBlaze should not be used with a Zynq device), connecting it to a serial port and some GPIOs, and running some sort of "Hello World" application on that? I created a project with a MicroBlaze and added a GPIO block, but am unsure what to do next to connect a UART either from the Zynq PS or add one to the fabric and route it to the pins that connect to the serial-to-USB on connector J14. I'm a software engineer, so my experience with these tools is somewhat minimal, so I need a bit of hand-holding. If there is an example project I can import for the ZedBoard, that might help, too. Thanks for all the help so far.

I'm still having a number of problems. Maybe I'm using the wrong wizard, but there is no "Refresh" button on the particular dialog that is showing up for me in Vivado 2021.1. I'm doing this on Linux (I was told by a co-worker that I should try installing under Linux). I choose "Create Project" and see an informational page, then click on the "Next>" button to get the following: Selecting "Example Project" (there seems to be no better choice offered), I select "Next>" and get: At this point, if I hit "Refresh", the left-side "Templates" panel clears, and I have to select the "vendor" checkbox in the "group by" drop-down on the upper-right corner of the Template toolbar to get this list back. I have tried "MicroBlaze Design Presets" and "Zynq-7000 Design Presets" (I've also looked at a few others) and hit "Next >", and I get something that looks like: No "Refresh" button. "Default board or part" only offers 2 choices, and I find no means of extending that list as shown in the screenshots provided. I get the sense that either Vivado 2021.1 has changed things around since those screenshots were taken, or I'm doing this all terribly wrong. I have the definite impression that I'm an idiot, and while that's probably true, I still need to get going with a MicroBlaze instance so I can be certain that I have a working FreeRTOS configuration prior to having to write custom drivers for the peripherals being designed for the next phase of this project. If anyone can point out what I'm doing wrong here, I'd appreciate it. Thanks. ---- Update: I noticed that the Tcl console on the main GUI has the following: So perhaps the lack of a "Refresh" button is because the GitHub repository has no board files updated for 2021.1; I'm not sure how to rectify this - I know Tcl well enough, but there's a lot of it in the various directories, and I'm pretty sure that changing things arbitrarily is not the key to a smooth experience.

I have a ZedBoard (Zynq XC7Z020) on which I wish to prototype some software on a MicroBlaze that will eventually be moved to a ZCU-102, and ultimately to a custom IO card. I was given the ZedBoard and installed the Xilinx software that came with it, but ISE 14.1 seems to have some trouble with Windows 10 (file selection dialogs don't always appear, and it can't seem to talk to the network very well), so I've installed Vivado 2021.1. Unfortunately, none of the directions I've found for installing the board files work properly under this version of the tools - it seems the stuff on GitHub (XilinxBoardStore / XilinxCEDStore) are not supported (I can't get them to work following the directions I've found, at least), and when I tried editing the Vivado start-up tcl script, the XML files appear available on the Diligent site seem to be incompatible (it breaks Vivado), so I cannot seem to create a project for the ZedBoard using Vivado 2021.1. There is a very nice Wiki page on the Diligent site that describes how to do it for the 2019 edition of the Xilinx tools, but it's out of date. Can anyone offer some advice on what I should do? Should I uninstall Vivado (both the 2021.1 and 14.1 versions) and try to download and install something in-between? This is on a Windows 10, 64-bit host. Thanks in advance. Sorry about typos and odd spacing (I've tried to clean it up as I type), but the laptop keyboard I'm using is not agreeing with my fingers, and I keep typing the wrong keys and extra spaces.

Hello. I'm an embedded software engineer who works closely with hardware and FPGA groups at an aerospace and defense company. I've been doing low-level platform work on and off since 1981, and try to keep up with the "latest" technologies, but I often lag behind. These days, I'm teaching myself VHDL and Verilog, and experimenting with soft core processors in FPGA fabric (also developing products utilizing them). I'm certain that I'll be asking all sorts of newbie questions in the technical forums. I'll also attempt to answer questions if I think I know enough about the subject at hand.