skinnypanda

awesome! thanks!

In asic design, I just put a request into our libary person to build a RAM the size I need, and get a module back with some behavioral code underneath. Not sure how it works in zedboard/vivado. I need a 4k x 16bit ram. and a much smaller 16 deep x 32bit wide ram. i coded them for a read port and a write port, but I could combine into one port if that helps. It needs to run at 100mhz. the 16x32 might be able to be built with flops. But I doubt the 4k block can be done in flops. do you just try to synthesize to see if flops will work? reg [31:0] smallram [15:0]; reg [15:0] bigram [4095:0]; Are there some modules that let me instantiate the underlying ram cells in the zedboard? I tried googling for zedboard block ram and found somethign that generates ram blocks with axi interfaces? That was more complicated than I needed. I was hoping for a paramaterized module that lets me specify width and depth? and a straightforward write/read bus, not AXI interface. I don't even know what to google. do you call that a block ram in vivado/zedboard speak? If this is already answered/explained somewhere else, just point me to it and I'll go there. thanks

" I had to do some digging to find them." I haven't been able to find anything at all. It's a bit odd how obscure this stuff is sometimes. "userInput = XUartPs_ReadReg(XPAR_PS7_UART_0_BASEADDR, XUARTPS_FIFO_OFFSET);" Yeah, that's pretty obscure. ;) But I was able to get this to work. ten lines of code and two very obscure calls, and it's doing what I need. thanks for the help.

Zygot:"Frankly if either of us has been abusive, it's been you. You are the only one slinging personal attacks." Yeah, lets do the instant replay: "What should we think of someone who asks for help, and oh by the way if this is complicated can I have a step by step tutorial, because my time is too important to find the answers for myself. And then, to the first person willing to give up his time to reply gets a 'how hard can it be?' retort? You wanna provide the punchline or should I?" There's an implication here that I am lazy, too important to google, and ungrateful enough to give a "retort". Unless the "punchline" was something complimentary? Yeah, no... That entire paragraph is the first salvo of personal attacks in this thread. You started this thread towards personal attacks. Not me. All i've done is ask a question, attempt to clarify that question after you misunderstood it, and then pointed out the above paragraph is when this thread started the personal attacks. The only time i ever said anything about you personally was when i pointed to your comments that were making personal attacks against me. Oh, and attacking someone by saying i think "my time is too important" and then pretending i am somehow "inferring things that aren't implied or explicitly written"? That is called gaslighting. You were very clear there, i think my time is too important, quite explicit, very personal, and when called on it, you pretend none of it happened. Gaslighting is when someone attacks and then tries to rewrite and rearrange history so they are the victim. So, a personal attack, followed by gaslighting. And the only thing i have said on this thread about you is pointing out where you started this thread down the path of personal attacks.

You misread my question, responding in what can only be descibed as toxic. And your invocation of "ironic humor" lands as someone saying "all in good fun!" after being abusive. I've been working as an engineer for decades. Most of it has been asic work. I am very rusty with fpga's. But i am no fool. And the sooner you get that people arent dumber than you just for asking a question, the better off you'll be.

"And then, to the first person willing to give up his time to reply gets a 'how hard can it be?' retort?" You said "you have parse the user input". and later you said "you will be into strings and conversions, and who knows what..." But that's way more complicated than I am looking for. I don't need to parse anything or deal with creating string classes. I tried to clarify that its a much more rudimentary problem by asking: "how hard would it be to print something, and then look for a "y" or "n" from the user?" There is clearly a misunderstanding going on here, and that was a legitimate attempt to clarify. "can I have a step by step tutorial, because my time is too important to find the answers for myself. " You have that exactly backwards. I said "If its complicated, could someone point me to a tutorial somewhere?" as in, if its complicated, but its covered somewhere already, then your time is too important to bother explaining it to a noob like me, just post the URL and I'll go wade through the answer there. this appears to be a continuation of the whole misunderstanding going on in this thread

how hard would it be to print something, and then look for a "y" or "n" from the user? I would have a small loop that checks to see if there is input available, and exit the loop when there is. Then get the character and see if its a "y" or "n". int answer; int wait4answer=1; while(wait4answer){ int wait4keyboard=1; while(wait4keyboard){ wait4keyboard = SOME_FUNCTION_TO_CHECK_IF_SERIAL_DATA_AVAILABLE(); } int char = SOME_FUNCTION_TO_GET_SERIAL_CHARACTER(); if((char=='y') || (char=='n')){ answer=char; wait4answer=0; } } DO_SOMETHING_WITH_ANSWER(answer); I've done something like this on simple microcontroller projects before. I just need to know what the SOME_FUNCTION_TO_CHECK_IF_SERIAL_DATA_AVAILABLE() and SOME_FUNCTION_TO_GET_SERIAL_CHARACTER() functions are called, assuming they exist. It doesn't have to present a shell type interface, it doesn't have to support up-arrow to get previous commands, or backspace to edit the current line of text, it doesn't have to do auto-complete when "tab" is hit.

I stepped through this tutorial and got it to work: http://islab.soe.uoguelph.ca/sareibi/TEACHING_dr/XILINX_VIVADO_dr/HwSw_dr/VivadoEmbeddedZyncTutorialAddIP.pdf It's a bare metal project that does writes and reads to a simple custom AXI IP block and then prints some info and results to serial terminal. I connect to zedboard with PUTTY on my PC, and when I run the code in vitis, it dumps a bunch of info to the terminal by calling print(). My question is how do I tweak this to do serial READ from the user serial terminal, but keep everything pretty much the same? If its complicated, could someone point me to a tutorial somewhere? I'm using vivado 2020.1, if that makes any difference. Thanks.

LED's are blinking and serial ports are talking! oooooh, MAN this feels good. thanks again for the help.

I deleted everything and started the tutorial over. I made sure every time vivado asked me to name a file or something, I prefixed it with "vivado_". and every vitis name was prefixed with "vitis_". It gave me a build. Don't know where, but somewhere I must have named something on top of an existing file and screwed things up quietly but deadly. Thanks for the help!

Just got myself a zedboard. says "copyright 2020" on the silkscreen so its fairly new. I'm stepping through the instructions here: https://reference.digilentinc.com/programmable-logic/guides/getting-started-with-ipi I'm using Vivado v2020.1 (64-bit), and Xilinx Vitis IDE v2020.1.0 (64-bit) because that seems to be the recommended version of tools for that tutorial. I tried a later version and a lot of the screenshots were completely different. When I get into vitis, I select the system project in the Assistant pane, and click the Build button (hammer). I get the following under the "Problems" tab: Description Resource Path Location Type fatal error: xgpio.h: No such file or directory main.c /project_1_app/src line 3 C/C++ Problem make: *** [makefile:38: package] Error 1 Debug /project_1_app_system C/C++ Problem When I look at the Vitis.log tab, I see the following, withi the zed.xsa error at the bottom: 12:45:48 DEBUG : Registering SDKStatusHandler to handle trace exceptions. 12:45:48 DEBUG : Registered the core plugin as the backup plugin for storing repository paths. 12:45:48 INFO : Launching XSCT server: xsct.bat -n -interactive D:\workspace\temp_xsdb_launch_script.tcl 12:45:48 INFO : XSCT server has started successfully. 12:45:48 INFO : plnx-install-location is set to '' 12:45:48 INFO : Successfully done setting XSCT server connection channel 12:45:48 INFO : Successfully done setting workspace for the tool. 12:45:48 INFO : Platform repository initialization has completed. 12:45:48 INFO : Registering command handlers for Vitis TCF services 12:45:48 INFO : Successfully done query RDI_DATADIR 12:45:57 INFO : Checking for BSP changes to sync application flags for project 'project_1_app'... 12:46:03 ERROR : (XSDB Server)ERROR: [Hsi 55-1571] The design file D:/workspace/project_1_wrapper/export/project_1_wrapper/hw/zed.xsa is already opened at which point, the Vitis.log stops there. I've seen the "fatal error: xgpio.h: No such file or directory" on other posts this forum and elsewhere, but I have not seen a definitive answer to how to fix it. The only specific "try this" thing I've seen is try refreshing and try going back to vivado and rerun synthesis, implementation, and bitstream. Neither fixed the problem for me. I followed these instructions to download board files: https://reference.digilentinc.com/programmable-logic/guides/installation I copied the "new/board files" because instructions say that is for versions later than 2014.4 And when I google for "zed.xsa is already opened", I don't find it anywhere. any help would be appreciated