skinnypanda

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  1. In asic design, I just put a request into our libary person to build a RAM the size I need, and get a module back with some behavioral code underneath. Not sure how it works in zedboard/vivado. I need a 4k x 16bit ram. and a much smaller 16 deep x 32bit wide ram. i coded them for a read port and a write port, but I could combine into one port if that helps. It needs to run at 100mhz. the 16x32 might be able to be built with flops. But I doubt the 4k block can be done in flops. do you just try to synthesize to see if flops will work? reg [31:0] smallram [15:0];
  2. " I had to do some digging to find them." I haven't been able to find anything at all. It's a bit odd how obscure this stuff is sometimes. "userInput = XUartPs_ReadReg(XPAR_PS7_UART_0_BASEADDR, XUARTPS_FIFO_OFFSET);" Yeah, that's pretty obscure. ;) But I was able to get this to work. ten lines of code and two very obscure calls, and it's doing what I need. thanks for the help.
  3. Zygot:"Frankly if either of us has been abusive, it's been you. You are the only one slinging personal attacks." Yeah, lets do the instant replay: "What should we think of someone who asks for help, and oh by the way if this is complicated can I have a step by step tutorial, because my time is too important to find the answers for myself. And then, to the first person willing to give up his time to reply gets a 'how hard can it be?' retort? You wanna provide the punchline or should I?" There's an implication here that I am lazy, too important to google, and ungrateful enough to
  4. You misread my question, responding in what can only be descibed as toxic. And your invocation of "ironic humor" lands as someone saying "all in good fun!" after being abusive. I've been working as an engineer for decades. Most of it has been asic work. I am very rusty with fpga's. But i am no fool. And the sooner you get that people arent dumber than you just for asking a question, the better off you'll be.
  5. "And then, to the first person willing to give up his time to reply gets a 'how hard can it be?' retort?" You said "you have parse the user input". and later you said "you will be into strings and conversions, and who knows what..." But that's way more complicated than I am looking for. I don't need to parse anything or deal with creating string classes. I tried to clarify that its a much more rudimentary problem by asking: "how hard would it be to print something, and then look for a "y" or "n" from the user?" There is clearly a misunderstanding going on here, and that was a legi
  6. how hard would it be to print something, and then look for a "y" or "n" from the user? I would have a small loop that checks to see if there is input available, and exit the loop when there is. Then get the character and see if its a "y" or "n". int answer; int wait4answer=1; while(wait4answer){ int wait4keyboard=1; while(wait4keyboard){ wait4keyboard = SOME_FUNCTION_TO_CHECK_IF_SERIAL_DATA_AVAILABLE(); } int char = SOME_FUNCTION_TO_GET_SERIAL_CHARACTER(); if((char=='y') || (char=='n')){ answer=char;
  7. I stepped through this tutorial and got it to work: http://islab.soe.uoguelph.ca/sareibi/TEACHING_dr/XILINX_VIVADO_dr/HwSw_dr/VivadoEmbeddedZyncTutorialAddIP.pdf It's a bare metal project that does writes and reads to a simple custom AXI IP block and then prints some info and results to serial terminal. I connect to zedboard with PUTTY on my PC, and when I run the code in vitis, it dumps a bunch of info to the terminal by calling print(). My question is how do I tweak this to do serial READ from the user serial terminal, but keep everything pretty much the same? If its complicat
  8. I deleted everything and started the tutorial over. I made sure every time vivado asked me to name a file or something, I prefixed it with "vivado_". and every vitis name was prefixed with "vitis_". It gave me a build. Don't know where, but somewhere I must have named something on top of an existing file and screwed things up quietly but deadly. Thanks for the help!
  9. Just got myself a zedboard. says "copyright 2020" on the silkscreen so its fairly new. I'm stepping through the instructions here: https://reference.digilentinc.com/programmable-logic/guides/getting-started-with-ipi I'm using Vivado v2020.1 (64-bit), and Xilinx Vitis IDE v2020.1.0 (64-bit) because that seems to be the recommended version of tools for that tutorial. I tried a later version and a lot of the screenshots were completely different. When I get into vitis, I select the system project in the Assistant pane, and click the Build button (hammer). I get the following u