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To elaborate on the signal integrity performance. Before each efuse programming, the production script read the FPGA DNA and the eFuse CNTL register to insure stable supply and good connection. We have not seen any issue with the DNA nor eFuse CNTL register read. We have no issue in the production with the FPGA image load which is substantial larger than the eFuse key. On a board which failed eFuse program, we have programmed the eFuse CNTL register over 10,000 times without issue. We will really appreciate if you have a TCL script which perform a read/write test sufficient to determine the signal integrity performance.

We know the signal integrity is perfect with the JTAG-SMT3-NC and we have intensively tested the read/write stability on a eFuse failed board, so we know it is not a signal integrity issue and it is too easy just to blame signal integrity. Do you have a read/write test which we can perform to prove whether there is a signal integrity or not?

Is there any news from Xilinx?

Do you have any news on which firmware version was qualified by Xilinx? Are there any options for a firmware version with additional timing margin under eFuse programming?

Thanks for the firmware version explanation, our Vivado version 2018.2 has "FTDIFW_57_00000001_00000000_010A-64bit.so" so thereby firmware version 1.10. Can you please check which firmware version was qualified by Xilinx? Would it be possible to get at firmware version with additional timing margin under eFuse programming? If not, it seems like we are forced to shift our productions setup to Xilinx DLC10 programmers as we never see issue with the DLC10 programmer.

Is it possible to downgrade the firmware in Digilent SMT3 to something similar to a Xilinx DLC10 programmer? Do you have multiple firmware versions for the Digilent SMT3 probe and how can I see the firmware version?

What is the status on this issue and are there any news?

I can’t share exact production data, but we have used the JTAG-SMT3-NC on more than thousand systems this year in production.

We see the issue with Virtex-7 P/N XC7VX330T.

It seems like there is a mismatch in your documentation, the documentation for both JTAG-HS2 and JTAG-SMT3-NC state both eFUSE programming is supported and not supported. Is eFUSE programming supported by both JTAG-HS2 and JTAG-SMT3-NC?

Hi The JTAG SMT3 is on an add-on board in the production jig, we are sure there is no signal integrity issue as we have thoroughly validated the setup and never see other failure than eFUSE programming failures. The productions setup has programmed thousands of systems without any failures under FPGA image load. We used several Xilinx FPGA families, but only see issue with the Vitex-7 and JTAG-SMT3-NC combination. Please notice we never see failures with the Xilinx DLC10 programmer.

In beginning of 2021 we replaced some of our Xilinx DLC10 programmers with JTAG-SMT3-NC in our production setup. We have over the past months seen eFUSE programming failures but only in the systems with the JTAG-SMT3-NC programmer. We only see failures Vitex-7 and with the JTAG-SMT3-NC. There are no failures doing FPGA image programming nor FPGA DNA read, so we have full confidence the issue is not related to signal integrity. Failure rate is low, about 1%, but the boards are scrap when the eFUSE programming fail, as it programming some of the bits. We use Vivado 2018.2 on Linux and we only see the issue with JTAG-SMT3-NC. Do you have known issues with JTAG-SMT3-NC eFUSE programming on Vitex-7?