kinshuks

Hi, I was trying to simulate some simple data read and write to the ddr3 ram present on the arty A7 (artix 7 35T). However, the simulation gets stuck once the processor reaches the instruction related to the external ram data operation. I can successfully simulate systems which don't have external ram connected. The process of running simulation is as follows : create block design create HDL wrapper bit stream generation export hardware (including bitstream) In vitis IDE, make a platform project and then an application project write the required code build the project to get the elf file add elf file as sources in the vivado project associate elf files with microblaze tclapp::xilinx::designutils::write_ip_integrator_testbench -addToProject to create testbench and then run simulation code snippet used for external ram data write (base address of external ram = 0x80000000). XGpio gpio; u32 led; XGpio_Initialize(&gpio, 0); XGpio_SetDataDirection(&gpio, 1, 0x00000000); u32 *eram; eram = (u32 *)0x80000000; led = 2; while (1) { XGpio_DiscreteWrite(&gpio, 2, led); eram[led] = led; } Please refer to the attached images of block design, simulation waveform and the dump of elf file. Vivado version - 2020.1 externalram_mb.zip