D@n

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Everything posted by D@n

  1. FFT

    @Weevil, I'm struggling to understand your picture. Can you explain for me what it is you are plotting? What is going into the FFT, and what is coming out? Even better, can you create a more complete trace showing the input and output FFT signaling as well? I'm hoping that would make your question easier to follow. Thanks! Dan
  2. Clarification for FFT implementation in FPGA

    Hi @subasheee, Congratulations! You are getting farther than many who have written to this blog. I often counsel folks not to use burst mode, such as you are using, but the pipeline mode instead. This is due to the added logic and complexity of properly setting up the valid and ready wires on the input, and the difficulty I personally have validating someone's design at a distance (i.e. via this forum). From what you've written above, it looks like you've solved and gotten past this problem. I'll hope so. You never told me the sample rate (or clock rate even) of the FFT. Are you running it at 1MHz? or 100MHz? (Best performance would be at 100MHz or so ...) But your question is about the FFT offset. You need to be aware that the first valid output from the FFT will not be the first sample out of the FFT, nor will it be the first sample one FFT length later. Look at the FFT manual--there's a flag that's used to note the first valid value from the FFT (and the last IIRC). You'll need to synch to that value, or you'll have these offset problems you noted above. As for whether or not you can buffer the incoming data ... of course you can! Will it help? That might depend upon what you are trying to do. I don't think you need to do this. Adjust the incoming valid signal instead, and the FFT should naturally buffer itself. Perhaps once you fill up the FFT you can give it a whole much of enable signals (I forget what the wire is called, CE perhaps?). You should be able to clock the Xilinx FFT at 100MHz or more. Your real driving factor in your computational delay is not the speed of the processing, but the speed of the input samples. As for resolution, an FFT is really a multi-rate signal processing tool. If you have samples coming in at 1MHz, but you want frequency resolution between 0-10 kHz, then you'll want to filter and downsample the FFT by a factor of (1MHz/20 kHz=) 50. Oh, back to resolution, don't forget that windowing can help. Hmm ... reading my comments above, they sound rather jumbled. Feel free to write back with more questions if this doesn't make any sense. Dan
  3. Questions about how to use UART

    @John_Anacall, One of the sad realities of a serial port is that one chips receiver is another's transmitter. Sometimes when the schematic calls it a receiver, it's a transmitter with respect to the FPGA chip, other times it's a receiver. Perhaps there's a way to know this answer by looking a the board, but I've made this as a mistake *so* many times, that I tend to use the "Hello World" demonstration program/design first (right after blinky) to make certain I have the transmit pin right before going farther. Reading over your post above, and your desire to build a GUI, my approach to FPGA's has always been through what I call a "debugging bus". This allows my software to interact with the FPGA by issuing read and write commands from c++ to register regions that I define on the FPGA. I have then used this link in the past to build a GUI, although it was terribly slow. (I was using the GUI to test an FFT with better frequency resolution--other than the speed, it worked quite well) One of the difficulties you will see across this forum with using the MicroBlaze microcontroller, is that 1) there are only a limited number of caned demos, 2) going beyond the canned demos isn't very clear, and 3) it's very difficult to debug when things go wrong--especially since you have no insight into what the micro is doing. On the other hand, if you started with an open source microcontroller, you'd have everything at your fingertips in order to debug it. You might even just run the whole thing in a simulator, and then see *EVERY* wire running through it. Just something to think about. Let me try explaining this another way. If you are familiar with software, and have a strong software background (it sounds like you do), then you can usually debug things via printf. FPGA's, however, are notoriously difficult to debug by printf. Yes, it is possible to debug the micro by printf---but not until 1) you have it up and running, and 2) your peripherals are work. As an example, on a recent design I was working on I messed up the the connection between a component and the system bus. I say this to point out that it isn't that uncommon. (I use WB bus, not an AXI bus, but bugs are not unique to WB) All of a sudden the design stopped responding to me, the serial port wouldn't work, and I had only the power button to fall back on. What was wrong with my design? Debug by printf wouldn't work. Debugging via other tools did, however. Just ... giving you some things to think about, Dan
  4. CMOD S6

    @jpeyron, Thanks for remembering! @IHATA, I'm still around, so ... you are more than welcome to ask questions about my S6 design. You can also read about some of the lessons I learned on my blog. This article, in particular, is about trimming tuning logic down in order to get it to fit. Indeed, I still pretty proud of being able to get a multi-tasking program onto the S6. Dan
  5. Questions about how to use UART

    @John_Anacall, If you are just starting with FPGA's for the first time, my recommendation would be to build a UART without the micro on board. This will help you get past your XDC questions as well. You can find my example project doing just this thing on github. Please consider this seriously. FPGA's are difficult enough to deal with. Before adding that micro, I *strongly* recommend that you learn the basics or you will quickly end up like so many other beginners with a design that doesn't work and ... unable to answer why not. As for the micro, why would you buy a nice board (and an expensive one too) and then fill it up with the LUTs necessary to do what you could've done for only $15 with just a cheap micro? This wasn't why you bought your FPGA board, now, was it? But to come back and answer your question, registers are assigned typically by the bus interconnect structure. Dan
  6. Fir compiler core as a decimation

    @ATIF JAVED, So .... your issue with the output of the FIR compiled decimator is that it doesn't remove the runup? Why not just remove it yourself? Either within your own logic or after you bring the filter's results back to your PC to examine? In many if not most of the signal processing applications I've dealt with, the signal is an infinite stream of numbers and the transient just washes out quickly--enough so that it's not really relevant. It seems like the FIR filter produced this type of result. There are other applications where the DSP is applied to a finite data set. It's just that these have been the exception rather than the rule in my humble experience. In these examples, the transient response becomes relevant. For testing a filter, knowing when/where the transient begins can be a difficulty. For testing a decimator, it can become even more of a challenge, as the test harness must now also know the phase of the decimator. Dan
  7. Nexys4 ddr Ethernet

    @flexible111, I think you misunderstand the purpose of the Digilent team. Their role is to provide just a demonstration that the boards work--enough that you can know there are no hardware failures. I think they've done that in this instance, and as I read the thread above that's exactly what @jpeyron was telling you. Your role is to program the board to make it do .... whatever it is you want your hardware to do. Do you know what it is you wish to do? What your ultimate goal is? That may be a worthwhile discussion on this forum. Will you be using IPv4? TCP or UDP protocols? If you are using the TCP protocol, then .... are you familiar with it? (I think this is what tera term uses--but I don't havve it to know.) Do you know how TCP works? Many FPGA designers choose to use UDP instead, since it is often easier to build with. Listening on a UDP port, though, takes a bit more work, and often a different application (netcat). Since you want to learn how to work with this network device, do you have wireshark installed? You might need it to know what is and isn't working. Dan
  8. Memory tutorial

    @dgottesm, This link has pictures. If your memory needs are simple, they can often be handled with block RAM. You can declare block RAM within your design, and you will find it *exceptionally* easy to use and access. The link above should discuss how to do a traditional FIFO in block RAM alone. If, on the other hand, you need more block RAM memory than your chip has ... that's when you need to turn to the DDR3 solution. I wouldn't touch it, though, if I only had a simple requirement. Dan
  9. Is this the correct file?

    @Newport_j, It's just a text file. Feel free to open it up in your favorite editor, make a back up copy and then edit it (You'll need to for most projects ...) Dan
  10. Memory tutorial

    @dgottesm, Working with DDR3 SDRAM is a common request on this forum--and the easy answer isn't very fulfilling, nor does it offer many further ideas to move from it. See this previous post for a discussion of this issue. Feel free to open up the .prj file for the Zybo to know what settings you might need, Dan
  11. Google Analytics

    @chuvke, I used to be very much against using Google Analytics, as you've expressed above. Indeed, I've still got Google Analytics blocked in all of my ad-block scripts--just 'cause I don't want people tracking me. Then I started blogging. Strangers started approaching me and talking to me about articles I had written. In many ways, I'd end up surprised ... really, you heard about that? Or, after I put a lot of energy into a post, sometimes I'd find links to that post around the web and then I'd wonder ... what happened? How many people really liked my posts? So I added Google Analytics to my site. I can now measure how many individuals are interested in my posts, and even see "events" when someone chooses to post an article on Hackaday.com or Hacker News. Knowing where my articles end up getting posted helps me get feedback for my articles as well, since I can see what others write about it. At the end of the year, I was even able to put together a top-10 list of articles people liked. It now helps me know what my audience is interested in. Were I Digilent (I'm not), I'd want this information as well--even more so, too, since they are selling their products via their web page. Their marketing group wants to know how many people are looking at which product, and which product they end up purchasing. They'd like to know if a product has an inferior design, if it is too hard to use, or if people don't realize the value of an item. These are all questions that Google Analytics can help recognize--although the forum helps as well. Now, to your question ... when I search through the Google-Analytics results on my own web site, Google-Analytics removes user information. As a result, I can't tell that @chuvke entered at this location, browsed in this fashion, and left. Instead, I can only tell that 156 of my users in the last week entered my site through this page, or 67 came through this other page, 66 through this page, and after their first interaction, 34 go on to read about FPGA Hell, 19 want to read what projects I'm working on and so forth. The web page (shown below) just ... doesn't reveal that much about users, but rather more about flow through the web-site. From my perspective, though--I hardly ever use this chart. Drilling through this data is just too difficult, but I would imagine Digilent is big enough to have someone look at this sort of stuff--I just don't know how they would make heads or tails of this, but I digress. I don't even have access to the IP address beyond a chart showing what nations people are viewing my site from. The real-time display (shown below) offers more--often down to the city level, but still not the actual IP address. I do know that there are some viewers who obscure this information. That's okay. I can respect their privacy, especially since it's only a small percentage of the viewers of my blog who do so. Browser, O/S, and screen size are also *very* important to any web-designer, as they help tell the web designer what screen sizes and browsers a particular page needs to be tested with to make certain it "looks" good. Indeed, some time ago I had to contact Digilent about a problem that kept me from being able to read key portions of a web page. Most customers won't do that, they'll just give up--that's the worst thing that can happen for a Vendor, for customers to struggle to learn about your product and therefore decide from a bad web-experience that they are not interested in it. Google Analytics tries to provide the web-designer the information necessary so they can do their own testing of pages to make certain they look good. In other words, while it might feel like you are being tracked by Digilent, as a Google Analytics user myself, I can say that from my own experience the reality of what takes place is far from any fears I had initially. Dan
  12. NEXYS 4 DDR

    @mamiko, Not sure I follow .... what question are you asking? Are you asking if folks on this forum will be willing to offer help? Yes, but they aren't willing to do your project for you. Yes indeed, there's a lot of help taking place on these forums. But ... if you want help, can you please be more specific about what you want help with? Thanks, Dan
  13. How to use DDR3 on Xilinx Arty board?

    @zygot, Did you read the link that comment pointed to? At the bottom is both a discussion of how much latency a DDR3 *should* have (as calculated by your most humble counterpart), and then a measurement of how much latency was measured in the AXI based MIG controller. Feel free to ask if you have questions, although further discussion on this topic should probably be kept to another thread. Dan
  14. How to use DDR3 on Xilinx Arty board?

    @smallpond_admin, It's a shame DDR3 SDRAM access is so complicated. This is partly due to the inherent complexity of the controller necessary to handle the SDRAM, and partly due to the high speeds involved. Digilent (not me) has tried to solve this issue by offering schematic based design solutions and tutorials, showing step by step how to get a fairly standard solution working. These tutorials are great, until you want to do something that's a bit off of the beaten path. Then, from my own observations of this forum, they fail miserably. I've tried a different solution. If you look at my own OpenArty project, I created the MIG controller and then interfaced to it from Verilog. When I found the AXI interface too complex, I bridged to it from a *MUCH* simpler wishbone interface. This has made reading and writing SDRAM fairly easy for me, although it is by no means all that fast. (The MIG controller has a very bad latency problem.) It works, it's open source, you are welcome to try it yourself. The problem with this approach is that it's not nearly as well documented as Digilent's approach--although I have put a document together describing how to set it up. Feel free to let me know if you wish to use this approach and run into any questions or problems, Dan
  15. Basys 3 vs Arty A7

    @Jaraqui Peixe, Looking at your description of what you need, it sounds like the Basys3 board is an ideal candidate for what you are looking for! It has VGA, 7-seg display, PS/2 mouse interface (which accepts a USB mouse--how cool is that?), can be programmed via USB stick, .... sounds like everything you want, right? Cool! I like to think of each board as a series of projects to be done. Combinational logic, sequential circuits, FSMs, etc, these can be done with *ANY* FPGA board you buy. 7-seg display's can be done with the Basys3, or even the Arty with an appropriate 7-segment display PMod purchase. Where the Arty really excels is in memory and the ethernet port. These are really great for CPU+logic designs, and it doesn't sound like you are looking for that feature. If your advanced students want to design their own CPU, the Basys3 will work for that as well--it's just that the limited block RAM will keep you from doing too much with it. The problem with the SDRAM on the Arty is that .... the controller necessary to use it is just *so* complex it's hard to teach what's going on to your students rather than just telling them to "trust me, it works." Somehow that doesn't seem all that satisfying, although many have done it and aren't bothered by it. The other thing the Arty has that the Basys3 doesn't is color LEDs--still, not a deal breaker or maker one way or another. My point being (and I don't represent Digilent, so don't sue me) the Basys3 sounds exactly like what you are looking for--if for no other reason than it has the 7segment display already installed, and a VGA is just such a *wonderful* show+tell example of FSMs ... you'll enjoy seeing your students faces light up when they see what's on the screen. Dan
  16. PMOD OLED how to send char to display

    @Riesenrad, Nevermind, it's been so long I had forgotten how I had implemented it. I was trying to refer to this part of the code, but looking back at it now I see that it doesn't use the DMA at all. Dan
  17. PMOD OLED how to send char to display

    @Riesenrad You could ... My own code included a DMA reference to copy an image to the display. You'll probably want to replace that with something of your own choosing as well, Dan
  18. PMOD OLED how to send char to display

    @Riesenrad, I programmed the OLEDrgb in C because it was convenient. There's no reason why you need to do the same--especially if you have different requirements (i.e.: no soft core), Dan
  19. FFT issue on ARTY Board

    @train04, You tell me, are the outputs correct? The proper way to debug any FPGA-based DSP algorithm is to run the algorithm in both hardware (Arty, although I like using the software emulator Verilator) and software (Octave), and compare the results. When the results match, you know your hardware algorithm is working. Dan
  20. FFT issue on ARTY Board

    You might just wish to hold the IFFT in a reset state until the first valid output comes out of the FFT ... Dan
  21. FFT issue on ARTY Board

    @train04, Thanks, that resolves one possibility. You've still got alignment issues between your FFT and your IFFT. Dan
  22. PMOD OLED how to send char to display

    @Riesenrad, You can find all of my sources for the OLEDrgb as part of my OpenArty project. This includes the code to bring it up and display an image, as well as the Verilog code to make a (wishbone) bus-accessed peripheral of it. Dan
  23. Announce: LabToy 0v1 (CMOD A7 35T board)

    @xc6lx45, Hey, that looks pretty cool! Thanks for sharing, Dan
  24. FFT issue on ARTY Board

    @train04, I almost missed that you'd sent something to me. Do me a favor ... when you want to get my attention, type the "@" sign followed by my screen name, "D@n". The forum will then give you a menu with my name on it. Select my name. The result should look something like @D@n. That'll let me know you wrote something that you wanted me to take a look at. With that out of the way, let's see what we can learn from the image you just posted. Something looks wrong with your DDS output. If you zoom in on it, does that look like a sine wave? From here it looks like ... something else, like perhaps you didn't get the bit assignments right--I can't quite tell. It might be right--I just can't tell at this zoom setting. Judging from the FFT output, it looks like you are getting two impulses out per FFT, one on (hopefully) bin 205 or so and another on bin 1843 or so. There's a real trick to getting an IFFT to work following an FFT. It's simple in matlab or C/C++, no so simple in RTL. In particular, you need to make certain the two are aligned. From what you are showing above, I'm not certain this is the case. Were the channels misaligned, bin 205 and bin 1843 might two lose their alignment and become two separate frequencies beating against each other. That looks like what you have going on here. The impulses coming out of the inverse FFT are puzzling me. They suggest that you have a touch of a bias going into the IFFT, perhaps your samples aren't centered around zero as you'd like? Again, I can't tell from here. One of the things I like to do when debugging FFT's is to pull the (output) sample values into a program where I can examine them--perhaps Matlab or Octave. You should then be able to take your own FFT (within Matlab or Octave) and compare it with the results you are getting. Plot both methods on your screen at the same time. That'll help you "see" visually whether one method has a problem or not. Dan
  25. FIFO CDC and Gray codes

    @zygot, You might consider reading the paper I referenced. It's worth the read. Dan